The Experts below are selected from a list of 81942 Experts worldwide ranked by ideXlab platform
Koen De Bosschere - One of the best experts on this subject based on the ideXlab platform.
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efficient Design space exploration of high performance embedded out of order Processors
Design Automation and Test in Europe, 2006Co-Authors: Stijn Eyerman, Koen De BosschereAbstract:Previous work on efficient customized Processor Design primarily focused on in-order architectures. However, with the recent introduction of out-of-order Processors for high-end high-performance embedded applications, researchers and Designers need to address how to automate the Design process of customized out-of-order Processors. Because of the parallel execution of independent instructions in out-of-order Processors, in-order Processor Design methodologies which subdivide the search space in independent components are unlikely to be effective in terms of accuracy for Designing out-of-order Processors. In this paper we propose and evaluate various automated singleand multi-objective optimizations for exploring out-of-order Processor Designs. We conclude that the newly proposed genetic local search algorithm outperforms all other search algorithms in terms of accuracy. In addition, we propose two-phase simulation in which the first phase explores the Design space through statistical simulation; a region of interest is then simulated through detailed simulation in the second phase. We show that simulation time speedups can be obtained of a factor 2.2times to 7.3times using two-phase simulation
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control flow modeling in statistical simulation for accurate and efficient Processor Design studies
International Symposium on Computer Architecture, 2004Co-Authors: Lieven Eeckhout, Koen De Bosschere, Robert H Bell, Bastiaan Stougie, Lizy K JohnAbstract:Designing a new microProcessor is extremely time-consuming.One of the contributing reasons is that computerDesigners rely heavily on detailed architectural simulations,which are very time-consuming. Recent workhas focused on statistical simulation to address this issue.The basic idea of statistical simulation is to measurecharacteristics during program execution, generate asynthetic trace with those characteristics and then simulatethe synthetic trace. The statistically generated synthetictrace is orders of magnitude smaller than the original programsequence and hence results in significantly fastersimulation.This paper makes the following contributions to the statisticalsimulation methodology. First, we propose the useof a statistical flow graph to characterize the control flow ofa program execution. Second, we model delayed update ofbranch predictors while profiling program execution characteristics.Experimental results show that statistical simulationusing this improved control flow modeling attainssignificantly better accuracy than the previously proposedHLS system. We evaluate both the absolute and the relativeaccuracy of our approach for power/performance modelingof superscalar microarchitectures. The results showthat our statistical simulation framework can be used to efficientlyexplore Processor Design spaces.
John Shen - One of the best experts on this subject based on the ideXlab platform.
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modern Processor Design fundamentals of superscalar Processors
2002Co-Authors: John Shen, Mikko H LipastiAbstract:Modern Processor Design: Fundamentals of Superscalar Processors is an exciting new first edition from John Shen of Carnegie Mellon University & Intel and Mikko Lipasti of the University of Wisconsin-Madison. This book brings together the numerous microarchitectural techniques for harvesting more instruction-level parallelism (ILP) to achieve better Processor performance that have been proposed and implemented in real machines. These techniques, as well as the foundational principles behind them, are organized and presented within a clear framework that allows for ease of comprehension. This text is intended for an advanced computer architecture course or a course in superscalar Processor Design. It is written at a level appropriate for senior or first year graduate level students.
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a realistic study on multithreaded superscalar Processor Design
European Conference on Parallel Processing, 1997Co-Authors: Yuan C Chou, Daniel P. Siewiorek, John ShenAbstract:Simultaneous multithreading is a recently proposed technique in which instructions from multiple threads are dispatched and/or issued concurrently in every clock cycle. This technique has been claimed to improve the latency of multithreaded programs and the throughput of multiprogrammed workloads with a minimal increase in hardware complexity. This paper presents a realistic study on the case for simultaneous multithreading by using extensive simulations to determine balanced configurations of a multithreaded version of the PowerPC 620, measuring their performance on multithreaded benchmarks written using the commercial P Threads API, and estimating their hardware complexity in terms of increases in die area. Our results show that a balanced 2- threaded 620 achieves a 41.6% to 71.3% speedup over the original 620 on five multithreaded benchmarks with an estimated 36.4% increase in die area and no impact on single thread performance. The balanced 4-threaded 620 achieves a 46.9% to 111.6% speedup over the original 620 with an estimated 70.4% increase in die area and a detrimental impact on single thread performance.
Josep Torrellas - One of the best experts on this subject based on the ideXlab platform.
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patching Processor Design errors with programmable hardware
IEEE Micro, 2007Co-Authors: Smruti R Sarangi, Abhishek Tiwari, Satish Narayanasamy, B Carneal, Brad Calder, Josep TorrellasAbstract:Equipping Processors with programmable hardware to patch Design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected, the manufacturer creates a fingerprint, which the customer uses to program the hardware. The hardware watches for error conditions; when they arise, it takes action to avoid the error. Overall, our scheme enables an exciting new environment where hardware Design errors can be handled as easily as system software bugs, by applying a patch to the hardware
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phoenix detecting and recovering from permanent Processor Design bugs with programmable hardware
International Symposium on Microarchitecture, 2006Co-Authors: Smruti R Sarangi, Abhishek Tiwari, Josep TorrellasAbstract:Although Processor Design verification consumes ever-increasing resources, many Design defects still slip into production silicon. In a few cases, such bugs have caused expensive chip recalls. To truly improve productivity, hardware bugs should be handled like system software ones, with vendors periodically releasing patches to fix hardware in the field. Based on an analysis of serious Design defects in current AMD, Intel, IBM, and Motorola Processors, this paper proposes and evaluates Phoenix -- novel field-programmable on-chip hardware that detects and recovers from Design defects. Phoenix taps key logic signals and, based on downloaded defect signatures, combines the signals into conditions that flag defects. On defect detection, Phoenix flushes the pipeline and either retries or invokes a customized recovery handler. Phoenix induces negligible slowdown, while adding only 0.05% area and 0.48% wire overheads. Phoenix detects all the serious defects that are triggered by concurrent control signals. Moreover, it recovers from most of them, and simplifies recovery for the rest. Finally, we present an algorithm to automatically size Phoenix for new Processors.
Wan-chi Siu - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - A new 3-phase Design exploration methodology for video Processor Design
2012 IEEE International Symposium on Circuits and Systems, 2012Co-Authors: Daniel P. K. Lun, Wan-chi SiuAbstract:When making video Processor Design, conventional Design exploration methodologies take extremely long time in parameter optimization but the final Design may not necessarily meet the application requirements since the architecture cannot deviate too much from the initial Design. To speed up the Design process, statistical performance models were used to guide the simulation; however their accuracy is questionable. In this paper, a new 3-phase Design exploration methodology for video Processor is proposed. It makes use of an almost cycle-accurate performance model to provide information for refining the Processor architecture. It can derive the optimal architecture in a much shorter period of time than the conventional methods. We successfully implemented a few video coding/decoding applications on the video Processor derived from the proposed methodology. Simulation results show that it outperforms other video Processors in both cost and performance perspectives.
Matthew J Thazhuthaveetil - One of the best experts on this subject based on the ideXlab platform.
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a predictive performance model for superscalar Processors
International Symposium on Microarchitecture, 2006Co-Authors: P J Joseph, Kapil Vaswani, Matthew J ThazhuthaveetilAbstract:Designing and optimizing high performance microProcessors is an increasingly difficult task due to the size and complexity of the Processor Design space, high cost of detailed simulation and several constraints that a Processor Design must satisfy. In this paper, we propose the use of empirical non-linear modeling techniques to assist Processor architects in making Design decisions and resolving complex trade-offs. We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative Design points spread across Processor Design space using latin hypercube sampling, (ii) obtaining performance measures at the selected Design points using detailed simulation, (iii) building non-linear models for performance using the function approximation capabilities of radial basis function networks, and (iv) validating the models using an independently and randomly generated set of Design points. We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural Design space that consists of 9 key parameters. Our results show that the models, built using a relatively small number of simulations, achieve high prediction accuracy (only 2.8% error in CPI estimates on average) across a large Processor Design space. Our models can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal Processor Design points.
