The Experts below are selected from a list of 25593 Experts worldwide ranked by ideXlab platform
Marly Roncken - One of the best experts on this subject based on the ideXlab platform.
-
an asynchronous Instruction length decoder
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Kenneth S Stevens, Shai Rotem, Ran Ginosar, Chris J Myers, C Dike, Peter A. Beerel, Marly RonckenAbstract:This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microProcessor architecture. A prototype complex Instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX Instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 Instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.
-
rappid an asynchronous Instruction length decoder
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
-
ASYNC - RAPPID: an asynchronous Instruction length decoder
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
Kenneth S Stevens - One of the best experts on this subject based on the ideXlab platform.
-
an asynchronous Instruction length decoder
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Kenneth S Stevens, Shai Rotem, Ran Ginosar, Chris J Myers, C Dike, Peter A. Beerel, Marly RonckenAbstract:This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microProcessor architecture. A prototype complex Instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX Instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 Instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.
-
rappid an asynchronous Instruction length decoder
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
-
ASYNC - RAPPID: an asynchronous Instruction length decoder
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
Ran Ginosar - One of the best experts on this subject based on the ideXlab platform.
-
an asynchronous Instruction length decoder
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Kenneth S Stevens, Shai Rotem, Ran Ginosar, Chris J Myers, C Dike, Peter A. Beerel, Marly RonckenAbstract:This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microProcessor architecture. A prototype complex Instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX Instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 Instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.
-
rappid an asynchronous Instruction length decoder
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
-
ASYNC - RAPPID: an asynchronous Instruction length decoder
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
Shai Rotem - One of the best experts on this subject based on the ideXlab platform.
-
an asynchronous Instruction length decoder
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Kenneth S Stevens, Shai Rotem, Ran Ginosar, Chris J Myers, C Dike, Peter A. Beerel, Marly RonckenAbstract:This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microProcessor architecture. A prototype complex Instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX Instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 Instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.
-
rappid an asynchronous Instruction length decoder
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
-
ASYNC - RAPPID: an asynchronous Instruction length decoder
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
C Dike - One of the best experts on this subject based on the ideXlab platform.
-
an asynchronous Instruction length decoder
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Kenneth S Stevens, Shai Rotem, Ran Ginosar, Chris J Myers, C Dike, Peter A. Beerel, Marly RonckenAbstract:This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microProcessor architecture. A prototype complex Instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX Instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 Instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.
-
rappid an asynchronous Instruction length decoder
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
-
ASYNC - RAPPID: an asynchronous Instruction length decoder
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1999Co-Authors: Shai Rotem, Kenneth S Stevens, Ran Ginosar, Chris J Myers, C Dike, Marly Roncken, Peter A. Beerel, B AgapievAbstract:This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(R) Processor Instruction Decoder"), a prototype IA32 Instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 /spl mu/ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 Instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit.
