The Experts below are selected from a list of 210 Experts worldwide ranked by ideXlab platform

James E Smith - One of the best experts on this subject based on the ideXlab platform.

  • HiPEAC - Studying compiler optimizations on superscalar Processors through interval analysis
    High Performance Embedded Architectures and Compilers, 2008
    Co-Authors: Stijn Eyerman, Lieven Eeckhout, James E Smith
    Abstract:

    Understanding the performance impact of compiler optimizations on superscalar Processors is complicated because compiler optimizations interact with the microarchitecture in complex ways. This paper analyzes this interaction using interval analysis, an analytical Processor Model that allows for breaking total execution time into cycle components. By studying the impact of compiler optimizations on the various cycle components, one can gain insight into how compiler optimizations affect out-of-order Processor performance. The analysis provided in this paper reveals various interesting insights and suggestions for future work on compiler optimizations for out-of-order Processors. In addition, we contrast the effect compiler optimizations have on out-of-order versus in-order Processors.

  • IEEE PACT - Modeling Superscalar Processors via Statistical Simulation
    Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 1
    Co-Authors: Sébastien Nussbaum, James E Smith
    Abstract:

    Abstract: Statistical simulation is a technique for fast performance evaluation of superscalar Processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple Processor Model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of Modeling complexity. Both errors and convergence properties are studied in detail. A simple instruction Model yields an average error of 8% compared with detailed simulation. A more detailed instruction Model reduces the error to 5% but requires about three times as long to converge.

J E Smith - One of the best experts on this subject based on the ideXlab platform.

  • A first-order superscalar Processor Model
    Proceedings. 31st Annual International Symposium on Computer Architecture 2004., 2004
    Co-Authors: T.s. Karkhanis, J E Smith
    Abstract:

    A proposed performance Model for superscalar Processors consists of: 1) a component that Models the relationship between instructions issued per cycle and the size of the instruction window under ideal conditions; and 2) methods for calculating transient performance penalties due to branch mispredictions, instruction cache misses, and data cache misses. Using trace-derived data dependence information, data and instruction cache miss rates, and branch miss-prediction rates as inputs, the Model can arrive at performance estimates for a typical superscalar Processor that are within 5.8% of detailed simulation on average and within 13% in the worst case. The Model also provides insights into the workings of superscalar Processors and long-term microarchitecture trends such as pipeline depths and issue widths.

T.s. Karkhanis - One of the best experts on this subject based on the ideXlab platform.

  • A first-order superscalar Processor Model
    Proceedings. 31st Annual International Symposium on Computer Architecture 2004., 2004
    Co-Authors: T.s. Karkhanis, J E Smith
    Abstract:

    A proposed performance Model for superscalar Processors consists of: 1) a component that Models the relationship between instructions issued per cycle and the size of the instruction window under ideal conditions; and 2) methods for calculating transient performance penalties due to branch mispredictions, instruction cache misses, and data cache misses. Using trace-derived data dependence information, data and instruction cache miss rates, and branch miss-prediction rates as inputs, the Model can arrive at performance estimates for a typical superscalar Processor that are within 5.8% of detailed simulation on average and within 13% in the worst case. The Model also provides insights into the workings of superscalar Processors and long-term microarchitecture trends such as pipeline depths and issue widths.

Sébastien Nussbaum - One of the best experts on this subject based on the ideXlab platform.

  • IEEE PACT - Modeling Superscalar Processors via Statistical Simulation
    Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 1
    Co-Authors: Sébastien Nussbaum, James E Smith
    Abstract:

    Abstract: Statistical simulation is a technique for fast performance evaluation of superscalar Processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple Processor Model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of Modeling complexity. Both errors and convergence properties are studied in detail. A simple instruction Model yields an average error of 8% compared with detailed simulation. A more detailed instruction Model reduces the error to 5% but requires about three times as long to converge.

Frédéric Vivien - One of the best experts on this subject based on the ideXlab platform.

  • Minimizing the Stretch When Scheduling Flows of Divisible Requests
    Journal of Scheduling, 2008
    Co-Authors: Arnaud Legrand, Frédéric Vivien
    Abstract:

    In this paper, we consider the problem of scheduling distributed biological sequence comparison applications. This problem lies in the divisible load framework with negligible communication costs. Thus far, very few results have been proposed for this Model. We discuss and select relevant metrics for this framework: namely max-stretch and sum-stretch. We explain the relationship between our Model and the preemptive single Processor case, and we show how to extend algorithms that have been proposed in the literature for the single Processor Model to the divisible multi-Processor problem domain. We recall known results on closely related problems, we show how to minimize the max-stretch on unrelated machines either in the divisible load Model or with preemption, we derive new lower bounds on the competitive ratio of any online algorithm, we present new competitiveness results for existing algorithms, and we develop several new online heuristics. We also address the Pareto optimization of max-stretch. Then, we extensively study the performance of these algorithms and heuristics under realistic scenarios. Our study shows that all previously proposed guaranteed heuristics for max-stretch for the single Processor Model are inefcient in practice. In contrast, we show that our online algorithms based on linear programming are in practice near-optimal solutions for max-stretch. Our study also clearly suggests heuristics that are efcient for both metrics, although a combined optimization is in theory not possible in the general case.

  • Minimizing the Stretch When Scheduling Flows of Biological Requests
    2006
    Co-Authors: Arnaud Legrand, Frédéric Vivien
    Abstract:

    In this paper, we consider the problem of scheduling comparisons of motifs against biological databanks. distributed biological sequence comparison applications. This problem lies in the divisible load framework with negligible communication costs. Thus far, very few results have been proposed in this Model. We discuss and select relevant metrics for this framework: namely max-stretch and sum-stretch. We explain the relationship between our Model and the preemptive uni-Processor case, and we show how to extend algorithms that have been proposed in the literature for the uni-Processor Model to the divisible multi-Processor problem domain. We recall known results on closely related problems, derive new lower bounds on the competitive ratio of any on-line algorithm, present new competitiveness results for existing algorithms, and develop several new on-line heuristics. Then, we extensively study the performance of these algorithms and heuristics in realistic scenarios. Our study shows that all previously proposed guaranteed heuristics for max-stretch for the uni-Processor Model prove to be particularly inefficient in practice. In contrast, we show our on-line algorithms based on linear programming to be near-optimal solutions for max-stretch. Our study also clearly suggests heuristics that are efficient for both metrics, although a combined optimization is in theory not possible in the general case.

  • Minimizing the stretch when scheduling flows of divisible requests
    2006
    Co-Authors: Arnaud Legrand, Frédéric Vivien
    Abstract:

    In this paper, we consider the problem of scheduling distributed biological sequence comparison applications. This problem lies in the divisible load framework with negligible communication costs. Thus far, very few results have been proposed in this Model. We discuss and select relevant metrics for this framework: namely max-stretch and sum-stretch. We explain the relationship between our Model and the preemptive uni-Processor case, and we show how to extend algorithms that have been proposed in the literature for the uni-Processor Model to the divisible multi-Processor problem domain. We recall known results on closely related problems, we show how to minimize the max-stretch on unrelated machines either in the divisible load Model or with preemption, we derive new lower bounds on the competitive ratio of any on-line algorithm, we present new competitiveness results for existing algorithms, and we develop several new on-line heuristics. We also address the Pareto optimization of max-stretch. Then, we extensively study the performance of these algorithms and heuristics in realistic scenarios. Our study shows that all previously proposed guaranteed heuristics for max-stretch for the uni-Processor Model prove to be inefficient in practice. In contrast, we show our on-line algorithms based on linear programming to be near-optimal solutions for max-stretch. Our study also clearly suggests heuristics that are efficient for both metrics, although a combined optimization is in theory not possible in the general case.

  • Minimizing the stretch when scheduling flows of biological requests
    2005
    Co-Authors: Arnaud Legrand, Frédéric Vivien
    Abstract:

    In this paper, we consider the problem of scheduling comparisons of motifs against biological databanks. This problem lies in the divisible load framework with negligible communication costs. Thus far, very few results have been proposed in this Model. We first explain the relationship between this Model and the preemptive uni-Processor one. After having selected a few relevant metrics (max-stretch and sum-stretch), we show how to extend algorithms that have been proposed in the literature for the uni-Processor Model to our setting. Then we extensively study the performance of these algorithms in realistic scenarios. Our study clearly suggest an efficient heuristic for each of the two metrics, though a combined optimization is in theory not possible in the general case.