The Experts below are selected from a list of 285 Experts worldwide ranked by ideXlab platform
Kang G Shin - One of the best experts on this subject based on the ideXlab platform.
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RTSS - Evaluation of the probability of dynamic failure and Processor Utilization for real-time systems
Proceedings. Real-Time Systems Symposium, 1Co-Authors: Michael H Woodbury, Kang G ShinAbstract:It is shown how to determine closed-form expressions for task scheduling delay and active task time distributions for any real-time system application, given a scheduling policy and task execution time distributions. The active task time denotes the total time a task is executing or waiting to be executed, including scheduling delays and resource contention delays. The distributions are used to determine the probability of dynamic failure and Processor Utilization, where the probability of dynamic failure is the probability that any task will not complete before its deadline. The opposing effects of decreasing the probability of dynamic failure and increasing Utilization are also addressed. The analysis first addresses workloads where all tasks are periodic, i.e., they are repetitively triggered at constant frequencies. It is then extended to include the arrival of asynchronously triggered tasks. The effects of asynchronous tasks on the probability of dynamic failure and Utilization are addressed. >
Keikichi Tamaru - One of the best experts on this subject based on the ideXlab platform.
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IPPS - A memory efficient array architecture for real-time motion estimation
Proceedings 11th International Parallel Processing Symposium, 1Co-Authors: Vasily G. Moshnyaga, Keikichi TamaruAbstract:A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with lower memory requirements. It features minimal I/O pin count, 100% Processor Utilization and is quite suitable for VLSI implementation.
Andreas Muth - One of the best experts on this subject based on the ideXlab platform.
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Improving Processor Utilization with a task classification model based application specific hard real-time architecture
Proceedings Fourth International Workshop on Real-Time Computing Systems and Applications, 1997Co-Authors: G. Farber, T. Kolloch, F. Fischer, Andreas MuthAbstract:Modern microProcessors with caches and pipelines show increasing performance, but at the price of a decreasing predictability of execution times. The design of hard real time systems however has to be based on worst case considerations. Consequently, real-time systems are generally oversized and fail to profit of developments in the standard Processor field. This paper presents an approach where real-time systems are analyzed and built according to a task classification model. Each class of tasks corresponds to a type of Processor best suited in terms of performance and deterministic execution times. The resulting target architecture framework is a tightly coupled heterogeneous multiProcessor system based on templates using off-the-shelf components. The described real-time system design process includes a schedulability analysis method that supports the partitioning and allocation process and provides the necessary real-time guarantees. The result is a event-driven hard real-time system with improved Processor Utilization that will provably meet all its deadlines. A rapid prototyping platform implementing this concept is presented as well as application examples.
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RTCSA - Improving Processor Utilization with a task classification model based application specific hard real-time architecture
Proceedings Fourth International Workshop on Real-Time Computing Systems and Applications, 1Co-Authors: G. Farber, T. Kolloch, F. Fischer, Andreas MuthAbstract:Modern microProcessors with caches and pipelines show increasing performance, but at the price of a decreasing predictability of execution times. The design of hard real time systems however has to be based on worst case considerations. Consequently, real-time systems are generally oversized and fail to profit of developments in the standard Processor field. This paper presents an approach where real-time systems are analyzed and built according to a task classification model. Each class of tasks corresponds to a type of Processor best suited in terms of performance and deterministic execution times. The resulting target architecture framework is a tightly coupled heterogeneous multiProcessor system based on templates using off-the-shelf components. The described real-time system design process includes a schedulability analysis method that supports the partitioning and allocation process and provides the necessary real-time guarantees. The result is a event-driven hard real-time system with improved Processor Utilization that will provably meet all its deadlines. A rapid prototyping platform implementing this concept is presented as well as application examples.
Michael H Woodbury - One of the best experts on this subject based on the ideXlab platform.
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RTSS - Evaluation of the probability of dynamic failure and Processor Utilization for real-time systems
Proceedings. Real-Time Systems Symposium, 1Co-Authors: Michael H Woodbury, Kang G ShinAbstract:It is shown how to determine closed-form expressions for task scheduling delay and active task time distributions for any real-time system application, given a scheduling policy and task execution time distributions. The active task time denotes the total time a task is executing or waiting to be executed, including scheduling delays and resource contention delays. The distributions are used to determine the probability of dynamic failure and Processor Utilization, where the probability of dynamic failure is the probability that any task will not complete before its deadline. The opposing effects of decreasing the probability of dynamic failure and increasing Utilization are also addressed. The analysis first addresses workloads where all tasks are periodic, i.e., they are repetitively triggered at constant frequencies. It is then extended to include the arrival of asynchronously triggered tasks. The effects of asynchronous tasks on the probability of dynamic failure and Utilization are addressed. >
Vasily G. Moshnyaga - One of the best experts on this subject based on the ideXlab platform.
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IPPS - A memory efficient array architecture for real-time motion estimation
Proceedings 11th International Parallel Processing Symposium, 1Co-Authors: Vasily G. Moshnyaga, Keikichi TamaruAbstract:A new 2-D array architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the architecture ensures feasible solutions for the HDTV picture format with lower memory requirements. It features minimal I/O pin count, 100% Processor Utilization and is quite suitable for VLSI implementation.
