The Experts below are selected from a list of 108 Experts worldwide ranked by ideXlab platform
Jihong Kim - One of the best experts on this subject based on the ideXlab platform.
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exploiting process similarity of 3d flash memory for high performance ssds
International Symposium on Microarchitecture, 2019Co-Authors: Youngseop Shim, Jisung Park, Myungsuk Kim, Myoungjun Chun, Yoona Kim, Jihong KimAbstract:3D NAND flash memory exhibits two contrasting process characteristics from its manufacturing process. While process variability between different horizontal layers are well known, little has been systematically investigated about strong process similarity (PS) within the horizontal layer. In this paper, based on an extensive characterization study using real 3D flash chips, we show that 3D NAND flash memory possesses very strong process similarity within a 3D flash block: the word lines (WLs) on the same horizontal layer of the 3D flash block exhibit virtually equivalent reliability characteristics. This strong process similarity, which was not previously utilized, opens simple but effective new optimization opportunities for 3D flash memory. In this paper, we focus on exploiting the process similarity for improving the I/O latency. By carefully reusing various flash operating parameters monitored from accessing the leading WL, the remaining WLs on the same horizontal layer can be quickly accessed, avoiding unnecessary redundant steps for subsequent Program and read operations. We also propose a new Program Sequence, called mixed order scheme (MOS), for 3D NAND flash memory which can further reduce the Program latency. We have implemented a PS-aware FTL, called cubeFTL, which takes advantage of the proposed techniques. Our evaluation results show that cubeFTL can improve the IOPS by up to 48% over an existing PS-unaware FTL.
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improving performance and lifetime of nand storage systems using relaxed Program Sequence
Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
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DAC - Improving performance and lifetime of NAND storage systems using relaxed Program Sequence
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
Jisung Park - One of the best experts on this subject based on the ideXlab platform.
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exploiting process similarity of 3d flash memory for high performance ssds
International Symposium on Microarchitecture, 2019Co-Authors: Youngseop Shim, Jisung Park, Myungsuk Kim, Myoungjun Chun, Yoona Kim, Jihong KimAbstract:3D NAND flash memory exhibits two contrasting process characteristics from its manufacturing process. While process variability between different horizontal layers are well known, little has been systematically investigated about strong process similarity (PS) within the horizontal layer. In this paper, based on an extensive characterization study using real 3D flash chips, we show that 3D NAND flash memory possesses very strong process similarity within a 3D flash block: the word lines (WLs) on the same horizontal layer of the 3D flash block exhibit virtually equivalent reliability characteristics. This strong process similarity, which was not previously utilized, opens simple but effective new optimization opportunities for 3D flash memory. In this paper, we focus on exploiting the process similarity for improving the I/O latency. By carefully reusing various flash operating parameters monitored from accessing the leading WL, the remaining WLs on the same horizontal layer can be quickly accessed, avoiding unnecessary redundant steps for subsequent Program and read operations. We also propose a new Program Sequence, called mixed order scheme (MOS), for 3D NAND flash memory which can further reduce the Program latency. We have implemented a PS-aware FTL, called cubeFTL, which takes advantage of the proposed techniques. Our evaluation results show that cubeFTL can improve the IOPS by up to 48% over an existing PS-unaware FTL.
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improving performance and lifetime of nand storage systems using relaxed Program Sequence
Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
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DAC - Improving performance and lifetime of NAND storage systems using relaxed Program Sequence
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
Youngsun Song - One of the best experts on this subject based on the ideXlab platform.
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improving performance and lifetime of nand storage systems using relaxed Program Sequence
Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
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DAC - Improving performance and lifetime of NAND storage systems using relaxed Program Sequence
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
Sungjin Lee - One of the best experts on this subject based on the ideXlab platform.
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improving performance and lifetime of nand storage systems using relaxed Program Sequence
Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
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DAC - Improving performance and lifetime of NAND storage systems using relaxed Program Sequence
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
Jaeyong Jeong - One of the best experts on this subject based on the ideXlab platform.
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improving performance and lifetime of nand storage systems using relaxed Program Sequence
Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
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DAC - Improving performance and lifetime of NAND storage systems using relaxed Program Sequence
Proceedings of the 53rd Annual Design Automation Conference, 2016Co-Authors: Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong KimAbstract:We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new Program Sequence, called relaxed Program Sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
