The Experts below are selected from a list of 96 Experts worldwide ranked by ideXlab platform

Ingjer Huang - One of the best experts on this subject based on the ideXlab platform.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    IEEE Transactions on Computers, 2011
    Co-Authors: Chunhung Lai, Fuching Yang, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time Program Trace compressor, named Trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the Trace compressor, named the online mode, or exclusively as the Trace compressor, named the bypass mode. The RTL implementation of a 4 KB Trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the Trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address Trace as well.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    Design Automation Conference, 2009
    Co-Authors: Chunhung Lai, Fuching Yang, Chungfu Kao, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time Program Trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The Trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB Trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the Trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

  • a hardware approach to real time Program Trace compression for embedded processors
    IEEE Transactions on Circuits and Systems, 2007
    Co-Authors: Shyhming Huang, Ingjer Huang
    Abstract:

    Collecting the Program execution Traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real-time Program Traces are so huge such that real-time Program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress Program execution Traces in real time in order to reduce the Trace size. The approach consists of three modularized phases: 1) branch/target filtering; 2) branch/target address encoding; 3) Lempel-Ziv (LZ)-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real-time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1 to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1)

Chunhung Lai - One of the best experts on this subject based on the ideXlab platform.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    IEEE Transactions on Computers, 2011
    Co-Authors: Chunhung Lai, Fuching Yang, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time Program Trace compressor, named Trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the Trace compressor, named the online mode, or exclusively as the Trace compressor, named the bypass mode. The RTL implementation of a 4 KB Trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the Trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address Trace as well.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    Design Automation Conference, 2009
    Co-Authors: Chunhung Lai, Fuching Yang, Chungfu Kao, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time Program Trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The Trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB Trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the Trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

Fuching Yang - One of the best experts on this subject based on the ideXlab platform.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    IEEE Transactions on Computers, 2011
    Co-Authors: Chunhung Lai, Fuching Yang, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time Program Trace compressor, named Trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the Trace compressor, named the online mode, or exclusively as the Trace compressor, named the bypass mode. The RTL implementation of a 4 KB Trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the Trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address Trace as well.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    Design Automation Conference, 2009
    Co-Authors: Chunhung Lai, Fuching Yang, Chungfu Kao, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time Program Trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The Trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB Trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the Trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

Shyhming Huang - One of the best experts on this subject based on the ideXlab platform.

  • a hardware approach to real time Program Trace compression for embedded processors
    IEEE Transactions on Circuits and Systems, 2007
    Co-Authors: Shyhming Huang, Ingjer Huang
    Abstract:

    Collecting the Program execution Traces at full speed is essential to the analysis and debugging of real-time software behavior of a complex system. However, the generation rate and the size of real-time Program Traces are so huge such that real-time Program tracing is often infeasible without proper hardware support. This paper presents a hardware approach to compress Program execution Traces in real time in order to reduce the Trace size. The approach consists of three modularized phases: 1) branch/target filtering; 2) branch/target address encoding; 3) Lempel-Ziv (LZ)-based data compression. A synthesizable RTL code for the proposed hardware is constructed to analyze the hardware cost and speed and typical multimedia benchmarks are used to measure the compression results. The results show that our hardware is capable of real-time compression and achieving compression ratio of 454:1, far better than 5:1 achieved by typical existing hardware approaches. Furthermore, our modularized approach makes it possible to trade off between the hardware cost (typically from 1 to 50K gates) and the achievable compression ratio (typically from 5:1 to 454:1)

Chungfu Kao - One of the best experts on this subject based on the ideXlab platform.

  • a Trace capable instruction cache for cost efficient real time Program Trace compression in soc
    Design Automation Conference, 2009
    Co-Authors: Chunhung Lai, Fuching Yang, Chungfu Kao, Ingjer Huang
    Abstract:

    This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time Program Trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The Trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB Trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the Trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.