The Experts below are selected from a list of 147 Experts worldwide ranked by ideXlab platform
Dimitrios S. Nikolopoulos - One of the best experts on this subject based on the ideXlab platform.
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a comparison of Programming models for multiprocessors with explicitly managed memory hierarchies
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009Co-Authors: Scott Schneider, Jaeseung Yeom, Benjamin Rose, Adrian Sandu, John C. Linford, Dimitrios S. NikolopoulosAbstract:On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and error-prone even for expert programmers. Before we can allow compilers to handle this Complexity for us, we must identify the abstractions that are general enough to allow us to write applications with reasonable effort, yet specific enough to exploit the vast on-chip memory bandwidth of EMM multi-processors. To this end, we compare two Programming models against hand-tuned codes on the STI Cell, paying attention to programmability and performance. The first Programming model, Sequoia, abstracts the memory hierarchy as private address spaces, each corresponding to a parallel task. The second, Cellgen, is a new framework which provides OpenMP-like semantics and the abstraction of a shared address space divided into private and shared data. We compare three applications programmed using these models against their hand-optimized counterparts in terms of abstractions, Programming Complexity, and performance.
Scott Schneider - One of the best experts on this subject based on the ideXlab platform.
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a comparison of Programming models for multiprocessors with explicitly managed memory hierarchies
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009Co-Authors: Scott Schneider, Jaeseung Yeom, Benjamin Rose, Adrian Sandu, John C. Linford, Dimitrios S. NikolopoulosAbstract:On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and error-prone even for expert programmers. Before we can allow compilers to handle this Complexity for us, we must identify the abstractions that are general enough to allow us to write applications with reasonable effort, yet specific enough to exploit the vast on-chip memory bandwidth of EMM multi-processors. To this end, we compare two Programming models against hand-tuned codes on the STI Cell, paying attention to programmability and performance. The first Programming model, Sequoia, abstracts the memory hierarchy as private address spaces, each corresponding to a parallel task. The second, Cellgen, is a new framework which provides OpenMP-like semantics and the abstraction of a shared address space divided into private and shared data. We compare three applications programmed using these models against their hand-optimized counterparts in terms of abstractions, Programming Complexity, and performance.
Fabie Clermidy - One of the best experts on this subject based on the ideXlab platform.
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mcapi compliant hardware buffer manager mechanism to support communication in multi core architectures
Design Automation and Test in Europe, 2016Co-Authors: Thiago Raupp Da Rosa, Thomas Mesquida, Romai Lemaire, Fabie ClermidyAbstract:High performance and high power efficiency are two mandatory constraints for multi-core systems in order to successfully handle the most recent applications in several fields, e.g. image processing and communication standards. Nowadays, hardware accelerators are often used along with several processing cores to achieve the desired performance while keeping high power efficiency. However, such systems impose an increased Programming Complexity due to the lack of software standards that supports heterogeneity, frequently leading to custom solutions. On the other hand, implementing a standard software solution for embedded systems might induce significant overheads. This work presents a hardware mechanism in co-design with a standard Programming interface (API) for embedded systems focusing to decrease overheads imposed by software implementation while increasing programmability and communication performance. The results show gains of up to 97% in latency and an increase of 40 times in throughput for synthetic traffics and an average decrease of 95% in communication time for an image processing application.
Shangyou Zhang - One of the best experts on this subject based on the ideXlab platform.
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a stabilizer free weak galerkin finite element method on polytopal meshes
Journal of Computational and Applied Mathematics, 2020Co-Authors: Xiu Ye, Shangyou ZhangAbstract:Abstract A stabilizing/penalty term is often used in finite element methods with discontinuous approximations to enforce connection of discontinuous functions across element boundaries. Removing stabilizers from discontinuous Galerkin finite element methods will simplify formulations and reduce Programming Complexity significantly. The goal of this paper is to introduce a stabilizer free weak Galerkin (WG) finite element method for second order elliptic equations on polytopal meshes. This new WG method keeps a simple symmetric positive definite form and can work on polygonal/polyhedral meshes. Optimal order error estimates are established for the corresponding WG approximations in both a discrete H 1 norm and the L 2 norm. Numerical results are presented verifying the theorem.
James Tuck - One of the best experts on this subject based on the ideXlab platform.
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hardware supported persistent object address translation
International Symposium on Microarchitecture, 2017Co-Authors: Tiancong Wang, Sakthikumaran Sambasivam, Yan Solihin, James TuckAbstract:Emerging non-volatile main memory technologies create a new opportunity for writing programs with a large, byte-addressable persistent storage that can be accessed through regular memory instructions. These new memory-as-storage technologies impose significant challenges to current Programming models. In particular, some emerging persistent Programming frameworks, like the NVM Library (NVML), implement relocatable persistent objects that can be mapped anywhere in the virtual address space. To make this work, persistent objects are referenced using object identifiers (ObjectID), rather than pointers, that need to be translated to an address before the object can be read or written. Frequent translation from ObjectID to address incurs significant overhead. We propose treating ObjectIDs as a new persistent memory address space and provide hardware support for efficiently translating ObjectIDs to virtual addresses. With our design, a program can use load and store instructions to directly access persistent data using ObjectIDs, and these new instructions can reduce the Programming Complexity of this system. We also describe several possible microarchitectural designs and evaluate them. We evaluate our design on Sniper modeling both in-order and out-of-order processors with 6 micro-benchmarks and the TPC-C application. The results show our design can give significant speedup over the baseline system using software translation. We demonstrate for the Pipelined implementation that our design has an average speedup of 1.96X and 1.58X on an in-order and out-of-order processor, respectively, over the baseline system on microbenchmarks that place persistent data randomly into persistent pools. For the same in-order and out-of-order microarchitectures, we measure a speedup of 1.17X and 1.12X, respectively, on the TPC-C application when B+ Trees are put in different pools and rewritten to use our new hardware. CCS CONCEPTS • Computer systems organization → Superscalar architectures; • Hardware → Memory and dense storage;
