The Experts below are selected from a list of 5121 Experts worldwide ranked by ideXlab platform
Lianggee Chen - One of the best experts on this subject based on the ideXlab platform.
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generic ram based architectures for two dimensional discrete wavelet transform with line based method
IEEE Transactions on Circuits and Systems for Video Technology, 2005Co-Authors: Chaotsung Huang, Pochih Tseng, Lianggee ChenAbstract:In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive Pyramid Algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.
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generic ram based architecture for two dimensional discrete wavelet transform with line based method
Asia Pacific Conference on Circuits and Systems, 2002Co-Authors: Pochih Tseng, Chaotsung Huang, Lianggee ChenAbstract:In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive Pyramid Algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility.
M Vishwanath - One of the best experts on this subject based on the ideXlab platform.
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vlsi architectures for the discrete wavelet transform
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 1995Co-Authors: M Vishwanath, R M Owens, M J IrwinAbstract:A class of VLSI architectures based on linear systolic arrays, for computing the 1-D Discrete Wavelet Transform (DWT), is presented. The various architectures of this class differ only in the design of their routing networks, which could be systolic, semisystolic, or RAM-based. These architectures compute the Recursive Pyramid Algorithm, which is a reformulation of Mallat's Pyramid Algorithm for the DWT. The DWT is computed in real time (running DWT), using just N/sub w/(J-1) cells of storage, where N/sub w/ is the length of the filter and J is the number of octaves. They are ideally suited for single-chip implementation due to their practical I/O rate, small storage, and regularity. The N-point 1-D DWT is computed in 2N cycles. The period can be reduced to N cycles by using N/sub w/ extra MAC's. Our architectures are shown to be optimal in both computation time and in area. A utilization of 100% is achieved for the linear array. Extensions of our architecture for computing the M-band DWT are discussed. Also, two architectures for computing the 2-D DWT (separable case) are discussed. One of these architectures, based on a combination of systolic and parallel filters, computes the N/sup 2/-point 2-D DWT, in real time, in N/sup 2/+N cycles, using 2NN/sub w/ cells of storage. >
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the recursive Pyramid Algorithm for the discrete wavelet transform
IEEE Transactions on Signal Processing, 1994Co-Authors: M VishwanathAbstract:The recursive Pyramid Algorithm (RPA) is a reformulation of the classical Pyramid Algorithm (PA) for computing the discrete wavelet transform (DWT). The RPA computes the N-point DWT in real time (running DWT) using just L(log N/spl minus/1) words of storage, as compared with O(N) words required by the PA. L is the length of the wavelet filter. The RPA is combined with the short-length FIR filter Algorithms to reduce the number of multiplications and additions. >
Chaotsung Huang - One of the best experts on this subject based on the ideXlab platform.
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generic ram based architectures for two dimensional discrete wavelet transform with line based method
IEEE Transactions on Circuits and Systems for Video Technology, 2005Co-Authors: Chaotsung Huang, Pochih Tseng, Lianggee ChenAbstract:In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive Pyramid Algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.
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generic ram based architecture for two dimensional discrete wavelet transform with line based method
Asia Pacific Conference on Circuits and Systems, 2002Co-Authors: Pochih Tseng, Chaotsung Huang, Lianggee ChenAbstract:In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive Pyramid Algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility.
Pochih Tseng - One of the best experts on this subject based on the ideXlab platform.
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generic ram based architectures for two dimensional discrete wavelet transform with line based method
IEEE Transactions on Circuits and Systems for Video Technology, 2005Co-Authors: Chaotsung Huang, Pochih Tseng, Lianggee ChenAbstract:In this paper, three generic RAM-based architectures are proposed to efficiently construct the corresponding two-dimensional architectures by use of the line-based method for any given hardware architecture of one-dimensional (1-D) wavelet filters, including conventional convolution-based and lifting-based architectures. An exhaustive analysis of two-dimensional architectures for discrete wavelet transform in the system view is also given. The first proposed architecture is for 1-level decomposition, which is presented by introducing the categories of internal line buffers, the strategy of optimizing the line buffer size, and the method of integrating any 1-D wavelet filter. The other two proposed architectures are for multi-level decomposition. One applies the recursive Pyramid Algorithm directly to the proposed 1-level architecture, and the other one combines the two previously proposed architectures to increase the hardware utilization. According to the comparison results, the proposed architecture outperforms previous architectures in the aspects of line buffer size, hardware cost, hardware utilization, and flexibility.
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generic ram based architecture for two dimensional discrete wavelet transform with line based method
Asia Pacific Conference on Circuits and Systems, 2002Co-Authors: Pochih Tseng, Chaotsung Huang, Lianggee ChenAbstract:In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive Pyramid Algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility.
P K Meher - One of the best experts on this subject based on the ideXlab platform.
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memory efficient modular vlsi architecture for highthroughput and low latency implementation of multilevel lifting 2 d dwt
IEEE Transactions on Signal Processing, 2011Co-Authors: Basant Kumar Mohanty, P K MeherAbstract:In this paper, we present a modular and pipeline architecture for lifting-based multilevel 2-D DWT, without using line-buffer and frame-buffer. Overall area-delay product is reduced in the proposed design by appropriate partitioning and scheduling of the computation of individual decomposition-levels. The processing for different levels is performed by a cascaded pipeline structure to maximize the hardware utilization efficiency (HUE). Moreover, the proposed structure is scalable for high-throughput and area-constrained implementation. We have removed all the redundancies resulting from decimated wavelet filtering to maximize the HUE. The proposed design involves L Pyramid Algorithm (PA) units and one recursive Pyramid Algorithm (RPA) unit, where R=N/P , L=⌈log4P ⌉ and P is the input block size, M and N, respectively, being the height and width of the image. The entire multilevel DWT is computed by the proposed structure in MR cycles. The proposed structure has O(8R×2L) cycles of output latency, which is very small compared to the latency of the existing structures. Interestingly, the proposed structure does not require any line-buffer or frame-buffer, unlike the existing folded structures which otherwise require a line-buffer of size O(N) and frame-buffer of size O(M/2×N/2) for multilevel 2-D computation. Instead of those buffers, the proposed structure involves only local registers and RAM of size O(N). The saving of line-buffer and frame-buffer achieved by the proposed design is an important advantage, since the image size could very often be as large as 512 × 512. From the simulation results we find that, the proposed scalable structure offers better slice-delay-product (SDP) for higher throughput of implementation since the on-chip memory of this structure remains almost unchanged with input block size. It has 17% less SDP than the best of the corresponding existing structures on average, for different input-block sizes and image sizes. It involves 1.92 times more transistors, but offers 12.2 times higher throughput and consumes 52% less power per output (PPO) compared to the other, on average for different input sizes.
