The Experts below are selected from a list of 17625 Experts worldwide ranked by ideXlab platform
Akira Matsuzawa - One of the best experts on this subject based on the ideXlab platform.
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a cmos image sensor with analog two dimensional dct based compression circuits for one chip cameras
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, D Miyazaki, S Doushou, Akira MatsuzawaAbstract:This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable Quantization Level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8/spl times/8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable Level Quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-/spl mu/m CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB.
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a compressed digital output cmos image sensor with analog 2 d dct processors and adc quantizer
International Solid-State Circuits Conference, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, Akira MatsuzawaAbstract:Progress in CMOS-based image sensors is creating opportunities for a low-cost, low-power one-chip video camera with digitizing, signal processing and image compression. Such a smart camera head acquires compressed digital moving pictures directly into portable multimedia computers. Video encoders using a moving picture coding standard such as MPEG and H.26x are not always suitable for integration of image encoding on the image sensor, because of the complexity and the power dissipation. On-sensor image compression such as a CCD image sensor for lossless image compression and a CMOS image sensor with pixel-Level interframe coding are reported. A one-chip digital camera with on-sensor video compression is shown in the block diagram. The chip contains a 128/spl times/128-pixel sensor, 8-channel parallel read-out circuits, an analog 2-dimensional discrete cosine transform (2D DCT) processor and a variable Quantization-Level ADC (ADC/Q).
Shoji Kawahito - One of the best experts on this subject based on the ideXlab platform.
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a cmos image sensor with analog two dimensional dct based compression circuits for one chip cameras
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, D Miyazaki, S Doushou, Akira MatsuzawaAbstract:This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable Quantization Level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8/spl times/8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable Level Quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-/spl mu/m CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB.
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a compressed digital output cmos image sensor with analog 2 d dct processors and adc quantizer
International Solid-State Circuits Conference, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, Akira MatsuzawaAbstract:Progress in CMOS-based image sensors is creating opportunities for a low-cost, low-power one-chip video camera with digitizing, signal processing and image compression. Such a smart camera head acquires compressed digital moving pictures directly into portable multimedia computers. Video encoders using a moving picture coding standard such as MPEG and H.26x are not always suitable for integration of image encoding on the image sensor, because of the complexity and the power dissipation. On-sensor image compression such as a CCD image sensor for lossless image compression and a CMOS image sensor with pixel-Level interframe coding are reported. A one-chip digital camera with on-sensor video compression is shown in the block diagram. The chip contains a 128/spl times/128-pixel sensor, 8-channel parallel read-out circuits, an analog 2-dimensional discrete cosine transform (2D DCT) processor and a variable Quantization-Level ADC (ADC/Q).
Zaid Harchaoui - One of the best experts on this subject based on the ideXlab platform.
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divergence frontiers for generative models sample complexity Quantization Level and frontier integral
arXiv: Machine Learning, 2021Co-Authors: Lang Liu, Krishna Pillutla, Sean Welleck, Yejin Choi, Zaid HarchaouiAbstract:The spectacular success of deep generative models calls for quantitative tools to measure their statistical performance. Divergence frontiers have recently been proposed as an evaluation framework for generative models, due to their ability to measure the quality-diversity trade-off inherent to deep generative modeling. However, the statistical behavior of divergence frontiers estimated from data remains unknown to this day. In this paper, we establish non-asymptotic bounds on the sample complexity of the plug-in estimator of divergence frontiers. Along the way, we introduce a novel integral summary of divergence frontiers. We derive the corresponding non-asymptotic bounds and discuss the choice of the Quantization Level by balancing the two types of approximation errors arisen from its computation. We also augment the divergence frontier framework by investigating the statistical performance of smoothed distribution estimators such as the Good-Turing estimator. We illustrate the theoretical results with numerical examples from natural language processing and computer vision.
Yoshiaki Tadokoro - One of the best experts on this subject based on the ideXlab platform.
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a cmos image sensor with analog two dimensional dct based compression circuits for one chip cameras
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, D Miyazaki, S Doushou, Akira MatsuzawaAbstract:This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable Quantization Level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8/spl times/8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable Level Quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-/spl mu/m CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB.
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a compressed digital output cmos image sensor with analog 2 d dct processors and adc quantizer
International Solid-State Circuits Conference, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, Akira MatsuzawaAbstract:Progress in CMOS-based image sensors is creating opportunities for a low-cost, low-power one-chip video camera with digitizing, signal processing and image compression. Such a smart camera head acquires compressed digital moving pictures directly into portable multimedia computers. Video encoders using a moving picture coding standard such as MPEG and H.26x are not always suitable for integration of image encoding on the image sensor, because of the complexity and the power dissipation. On-sensor image compression such as a CCD image sensor for lossless image compression and a CMOS image sensor with pixel-Level interframe coding are reported. A one-chip digital camera with on-sensor video compression is shown in the block diagram. The chip contains a 128/spl times/128-pixel sensor, 8-channel parallel read-out circuits, an analog 2-dimensional discrete cosine transform (2D DCT) processor and a variable Quantization-Level ADC (ADC/Q).
K. Umehara - One of the best experts on this subject based on the ideXlab platform.
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a cmos image sensor with analog two dimensional dct based compression circuits for one chip cameras
IEEE Journal of Solid-state Circuits, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, D Miyazaki, S Doushou, Akira MatsuzawaAbstract:This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable Quantization Level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8/spl times/8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable Level Quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-/spl mu/m CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB.
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a compressed digital output cmos image sensor with analog 2 d dct processors and adc quantizer
International Solid-State Circuits Conference, 1997Co-Authors: Shoji Kawahito, Yoshiaki Tadokoro, K. Umehara, M Yoshida, Masaaki Sasaki, K Murata, Akira MatsuzawaAbstract:Progress in CMOS-based image sensors is creating opportunities for a low-cost, low-power one-chip video camera with digitizing, signal processing and image compression. Such a smart camera head acquires compressed digital moving pictures directly into portable multimedia computers. Video encoders using a moving picture coding standard such as MPEG and H.26x are not always suitable for integration of image encoding on the image sensor, because of the complexity and the power dissipation. On-sensor image compression such as a CCD image sensor for lossless image compression and a CMOS image sensor with pixel-Level interframe coding are reported. A one-chip digital camera with on-sensor video compression is shown in the block diagram. The chip contains a 128/spl times/128-pixel sensor, 8-channel parallel read-out circuits, an analog 2-dimensional discrete cosine transform (2D DCT) processor and a variable Quantization-Level ADC (ADC/Q).
