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Michael H Perrott - One of the best experts on this subject based on the ideXlab platform.
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a low Noise wide bw 3 6 ghz digital delta sigma fractional n frequency synthesizer with a Noise shaping time to digital converter and Quantization Noise cancellation
2008Co-Authors: Chunming Hsu, M Z Straayer, Michael H PerrottAbstract:A 3.6-GHz digital fractional-N frequency synthesizer achieving low Noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its Quantization Noise along with digital Quantization Noise cancellation to achieve integrated phase Noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-mum CMOS process, the prototype occupies 0.95-mm2 active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase Noise at 3.67 GHz carrier frequency is -108 and -150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.
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a low Noise wide bw 3 6ghz digital δσ fractional n frequency synthesizer with a Noise shaping time to digital converter and Quantization Noise cancellation
2008Co-Authors: Chunming Hsu, M Z Straayer, Michael H PerrottAbstract:A digital fractional-N frequency synthesizer is presented that leverages a Noise-shaping time-to-digital converter (TDC) and a simple Quantization Noise cancellation technique to achieve low phase Noise with a wide PLL bandwidth of 500kHz. In contrast to previous cancellation techniques, this structure requires no analog components and is straightforward to implement with standard-cell digital logic.
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a 1 mhz bandwidth 3 6 ghz 0 18 spl mu m cmos fractional n synthesizer utilizing a hybrid pfd dac structure for reduced broadband phase Noise
2006Co-Authors: Scott E Meninger, Michael H PerrottAbstract:A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase Noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N Quantization Noise. When compared to a classical second-order /spl Sigma//spl Delta/ synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB Quantization Noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase Noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.
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a 1 mhz bandwidth 3 6 ghz 0 18 μm cmos fractional n synthesizer utilizing a hybrid pfd dac structure for reduced broadband phase Noise
2006Co-Authors: Scott E Meninger, Michael H PerrottAbstract:A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase Noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N Quantization Noise. When compared to a classical second-order ΣΔ synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB Quantization Noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase Noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.
I Galton - One of the best experts on this subject based on the ideXlab platform.
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a class of quantizers with dc free Quantization Noise and optimal immunity to nonlinearity induced spurious tones
2013Co-Authors: Eythan Familier, Christian Venerus, I GaltonAbstract:Fractional- N phase-locked loops (PLLs) typically use Noise-shaping coarse quantizers to control their instantaneous output frequency. The resulting Quantization Noise and its running sum inevitably get distorted by non-ideal analog components within the PLL, which induces undesirable spurious tones in the PLL's output signal. A recently proposed quantizer, called a successive requantizer, has been shown to mitigate this problem. Its Quantization Noise and the running sum of its Quantization Noise can be subjected to up to fifth-order and third-order nonlinear distortion, respectively, without inducing spurious tones. This paper extends the previously published successive requantizer results to enable the design of successive requantizers whose Quantization Noise running sum sequences attain such immunity to nonlinearity-induced spurious tones up to arbitrarily high orders of distortion. The extended results are used to design example successive requantizers whose Quantization Noise and Quantization Noise running sum sequences have optimally reduced susceptibility to nonlinearity-induced spurious tones.
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a fundamental limitation of dc free Quantization Noise with respect to nonlinearity induced spurious tones
2013Co-Authors: Eythan Familier, I GaltonAbstract:Fractional-N phase-locked loops (PLLs) are widely used to synthesize local oscillator signals for modulation and demodulation in communication systems. Such PLLs generate and subsequently lowpass filter DC-free Quantization Noise as part of their normal operation. Unfortunately, the Quantization Noise and its running sum inevitably are subjected to nonlinear distortion from analog circuit imperfections which causes spurious tones in the PLL output signal that can degrade communication system performance. This paper presents the first general mathematical analysis of this phenomenon. It proves that if the running sum of the Quantization Noise, t[n], satisfies tlow <; t[n] ≤ thigh for all n, where tlow and thigh are integers, then subjecting t[n] to kth-order distortion for at least one k ∈ {1, 2, 3..., thigh - tlow} will result in spurious tones for most fractional-N PLL output frequencies regardless of how the Quantization is performed. It also shows that quantizers exist which are optimal in the sense that subjecting the running sum of their Quantization Noise to th-order distortion for any k ∈ {1, 2, 3..., thigh - tlow - 1} does not result in any spurious tones. In a typical fractional-N PLL, the larger the range of t[n] the greater the power of the PLL's phase Noise, so these results imply a fundamental tradeoff between phase Noise power and spurious tones in PLLs.
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statistics of the Quantization Noise in 1 bit dithered single quantizer digital delta sigma modulators
2007Co-Authors: Sudhakar Pamarti, J Welz, I GaltonAbstract:An analysis of the Quantization Noise introduced by a widely-used class of single-quantizer digital delta-sigma (DeltaSigma) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties of the Quantization Noise such as uniformity and independence from the input and delayed versions of itself. The conditions are also shown to be sufficient for a single realization of the Quantization Noise sequence to possess these properties in a time-averaged sense. Several of the most commonly-used digital DeltaSigma modulators are shown to satisfy the conditions
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granular Quantization Noise in a class of delta sigma modulators
1994Co-Authors: I GaltonAbstract:The trend toward digital signal processing in communication systems has resulted in a large demand for fast accurate analog-to-digital (A/D) converters, and advances in VLSI technology have made /spl Delta//spl Sigma/ modulator-based A/D converters attractive solutions. However, rigorous theoretical analyses have only been performed for the simplest /spl Delta//spl Sigma/ modulator architectures. Existing analyses of more complicated /spl Delta//spl Sigma/ modulators usually rely on approximations and computer simulations. In the paper, a rigorous analysis of the granular Quantization Noise in a general class of /spl Delta//spl Sigma/ modulators is developed. Under the assumption that some input-referred circuit Noise or dither is present, the second-order asymptotic statistics of the granular Quantization Noise sequences are determined and ergodic properties are derived. >
Yasushi Yamao - One of the best experts on this subject based on the ideXlab platform.
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Quantization Noise suppression for envelope pulse width modulation epwm transmitters
2010Co-Authors: Edwin M Umali, Shinsuke Yokozawa, Yasushi YamaoAbstract:The envelope pulse-width modulation (EPWM) transmitter has been proposed to address the issue of low power efficiency in the linear amplification of multicarrier signals such as the OFDM. However, the delta-sigma (Σ-Δ) modulator in the EPWM transmitter generates Quantization Noise that degrades signal quality. In this paper, two new EPWM architectures called the envelope subtraction EPWM (ES-EPWM) and the amplitude compensated EPWM (AC-EPWM) are proposed to enhance Quantization Noise suppression. The architectures generate a narrowband Noise-canceling signal that is either subtracted to the PWM envelope signal (ES-EPWM) or multiplied to the PM signal (AC-EPWM). Using the IEEE 802.11a OFDM signal, simulations were done with varying canceling signal bandwidth and oversampling ratio (OSR). Results showed that increasing the canceling signal bandwidth improved the performance of the ES-EPWM transmitter in terms of the measured error vector magnitude (EVM) and adjacent channel leakage power ratio (ACLR). A similar behavior was observed for the AC-EPWM transmitter, but only up to a certain canceling signal bandwidth. For an OSR of 32 and a canceling signal bandwidth of 40MHz, both ES-EPWM and AC-EPWM transmitters were able to improve the ACLR by 6 dB and reduce the EVM to 2/3.
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Quantization Noise and distortion analysis of envelope pulse width modulation epwm transmitters for ofdm signal amplification
2010Co-Authors: Edwin M Umali, Koji Kawazoe, Yasushi YamaoAbstract:The envelope pulse-width modulation (EPWM) transmitter has been proposed to address the power efficiency issue in the linear amplification of multicarrier signals. However, the delta-sigma (Δ-∑) modulator in the EPWM transmitter generates Quantization Noise that degrades the output signal quality. In this paper, Noise and distortion characteristics of the EPWM transmitter in the amplification of the OFDM signal are presented. First, Quantization Noise and distortion due to amplitude clipping are analyzed. Theoretical Noise power spectral density (PSD) and error vector magnitude (EVM) are obtained as functions of the Δ-∑ modulator and input signal parameters. Then, simulations to validate the Noise and distortion characteristics are done using the IEEE 802.11a OFDM signal and first- and second-order Δ-∑ modulators. The effects of bandpass filtering on EVM and adjacent channel leakage power ratio (ACLR) are also obtained by simulation. Results showed good agreement with the analytical results despite the use of the linear-approximation gain plus Noise model. The EPWM transmitter that employed the first-order Δ-∑ modulator with a 0.1% clipping probability, an oversampling ratio of 32 and a three-pole Butterworth bandpass filter yielded an EVM of 1.8% and an ACLR of -37.9 dB, which are sufficiently lower than the OFDM transmitter specification.
Scott E Meninger - One of the best experts on this subject based on the ideXlab platform.
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a 1 mhz bandwidth 3 6 ghz 0 18 spl mu m cmos fractional n synthesizer utilizing a hybrid pfd dac structure for reduced broadband phase Noise
2006Co-Authors: Scott E Meninger, Michael H PerrottAbstract:A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase Noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N Quantization Noise. When compared to a classical second-order /spl Sigma//spl Delta/ synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB Quantization Noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase Noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.
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a 1 mhz bandwidth 3 6 ghz 0 18 μm cmos fractional n synthesizer utilizing a hybrid pfd dac structure for reduced broadband phase Noise
2006Co-Authors: Scott E Meninger, Michael H PerrottAbstract:A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase Noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N Quantization Noise. When compared to a classical second-order ΣΔ synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB Quantization Noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase Noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.
Sudhakar Pamarti - One of the best experts on this subject based on the ideXlab platform.
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a 2 4 ghz wideband open loop gfsk transmitter with phase Quantization Noise cancellation
2011Co-Authors: Sudhakar PamartiAbstract:A wide-bandwidth phase modulation transmitter with phase Quantization Noise cancellation technique is proposed. Unlike conventional phase-locked loop closed-loop modulation, very wide-bandwidth arbitrary phase modulation can be synthesized at the phase-locked loop output by selecting the desired phases that are generated by a phase generator. To further reduce the phase Quantization Noise due to the finite number of available phases, a phase Quantization Noise cancellation path is proposed through a second VCO control port. At least 7 dB phase Noise cancellation was demonstrated using a prototype 0.18 μm CMOS 2.4 GHz GFSK transmitter integrated circuit. Measurements on the prototype show that out-of-band phase Quantization Noise is 49 dB lower than the signal when transmitting 20 Mb/s GFSK signal and that the rms error is only 3.2%. The current consumption is 34.5 mA excluding the transmitter output buffer.
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statistics of the Quantization Noise in 1 bit dithered single quantizer digital delta sigma modulators
2007Co-Authors: Sudhakar Pamarti, J Welz, I GaltonAbstract:An analysis of the Quantization Noise introduced by a widely-used class of single-quantizer digital delta-sigma (DeltaSigma) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties of the Quantization Noise such as uniformity and independence from the input and delayed versions of itself. The conditions are also shown to be sufficient for a single realization of the Quantization Noise sequence to possess these properties in a time-averaged sense. Several of the most commonly-used digital DeltaSigma modulators are shown to satisfy the conditions