The Experts below are selected from a list of 1572 Experts worldwide ranked by ideXlab platform
Seyed Amir Ali Danesh - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable 1 gsps to 250 msps 7 bit to 9 bit highly time interleaved counter adc with low power comparator design
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert HendersonAbstract:A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope Ramp-Generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.
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a reconfigurable 1gsps to 250msps 7 bit to 9 bit highly time interleaved counter adc in 0 13µm cmos
Symposium on VLSI Circuits, 2011Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert M HendersonAbstract:A reconfigurable highly time-interleaved ADC is realized by combining 128 counter ADCs and a global Ramp-Generator based on a rotating figure-of-8 resistor ring. Implemented in 0.13µm CMOS, the ADC can be configured in real-time as a 1GSps 7-bit, 500MSps 8-bit, and 250MSps 9-bit converter. It achieves sub 400fJ/step in all these configurations.
Robert M Henderson - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable 1gsps to 250msps 7 bit to 9 bit highly time interleaved counter adc in 0 13µm cmos
Symposium on VLSI Circuits, 2011Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert M HendersonAbstract:A reconfigurable highly time-interleaved ADC is realized by combining 128 counter ADCs and a global Ramp-Generator based on a rotating figure-of-8 resistor ring. Implemented in 0.13µm CMOS, the ADC can be configured in real-time as a 1GSps 7-bit, 500MSps 8-bit, and 250MSps 9-bit converter. It achieves sub 400fJ/step in all these configurations.
Keith Findlater - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable 1 gsps to 250 msps 7 bit to 9 bit highly time interleaved counter adc with low power comparator design
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert HendersonAbstract:A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope Ramp-Generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.
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a reconfigurable 1gsps to 250msps 7 bit to 9 bit highly time interleaved counter adc in 0 13µm cmos
Symposium on VLSI Circuits, 2011Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert M HendersonAbstract:A reconfigurable highly time-interleaved ADC is realized by combining 128 counter ADCs and a global Ramp-Generator based on a rotating figure-of-8 resistor ring. Implemented in 0.13µm CMOS, the ADC can be configured in real-time as a 1GSps 7-bit, 500MSps 8-bit, and 250MSps 9-bit converter. It achieves sub 400fJ/step in all these configurations.
Jed Hurwitz - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable 1 gsps to 250 msps 7 bit to 9 bit highly time interleaved counter adc with low power comparator design
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert HendersonAbstract:A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope Ramp-Generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.
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a reconfigurable 1gsps to 250msps 7 bit to 9 bit highly time interleaved counter adc in 0 13µm cmos
Symposium on VLSI Circuits, 2011Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert M HendersonAbstract:A reconfigurable highly time-interleaved ADC is realized by combining 128 counter ADCs and a global Ramp-Generator based on a rotating figure-of-8 resistor ring. Implemented in 0.13µm CMOS, the ADC can be configured in real-time as a 1GSps 7-bit, 500MSps 8-bit, and 250MSps 9-bit converter. It achieves sub 400fJ/step in all these configurations.
D Renshaw - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable 1 gsps to 250 msps 7 bit to 9 bit highly time interleaved counter adc with low power comparator design
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert HendersonAbstract:A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope Ramp-Generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.
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a reconfigurable 1gsps to 250msps 7 bit to 9 bit highly time interleaved counter adc in 0 13µm cmos
Symposium on VLSI Circuits, 2011Co-Authors: Seyed Amir Ali Danesh, Jed Hurwitz, Keith Findlater, D Renshaw, Robert M HendersonAbstract:A reconfigurable highly time-interleaved ADC is realized by combining 128 counter ADCs and a global Ramp-Generator based on a rotating figure-of-8 resistor ring. Implemented in 0.13µm CMOS, the ADC can be configured in real-time as a 1GSps 7-bit, 500MSps 8-bit, and 250MSps 9-bit converter. It achieves sub 400fJ/step in all these configurations.
