The Experts below are selected from a list of 645 Experts worldwide ranked by ideXlab platform
Zhong-ci Shi - One of the best experts on this subject based on the ideXlab platform.
-
TWO NONCONFORMING QUADRILATERAL ELEMENTS FOR THE REISSNER–MINDLIN PLATE
Mathematical Models and Methods in Applied Sciences, 2005Co-Authors: Pingbing Ming, Zhong-ci ShiAbstract:We construct two low order nonconforming quadrilateral elements for the Reissner–Mindlin plate. The first one consists of a modified nonconforming rotated Q1 element for one component of the rotation and the standard four-node isoparametric element for the other component as well as for the the approximation of the transverse displacement, a modified rotated Raviart–Thomas interpolation Operator is employed as the shear Reduction Operator. The second differs from the first only in the approximation of the rotation, which employs the modified rotated Q1 element for both components of the rotation, and a jump term accounting the discontinuity of the rotation approximation is included in the variational formulation. Both elements give optimal error bounds uniform in the plate thickness with respect to the energy norm as well as the L2 norm.
Henk Corporaal - One of the best experts on this subject based on the ideXlab platform.
-
Reduction Operator for wide simds reconsidered
Design Automation Conference, 2014Co-Authors: Luc Waeijen, Dongrui She, Henk CorporaalAbstract:It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, Reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require Reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs), which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support Reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel Reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% area with a performance penalty of only 6.5%.
-
DAC - Reduction Operator for Wide-SIMDs Reconsidered
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014Co-Authors: Luc Waeijen, Dongrui She, Henk CorporaalAbstract:It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, Reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require Reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs), which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support Reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel Reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% area with a performance penalty of only 6.5%.
Pingbing Ming - One of the best experts on this subject based on the ideXlab platform.
-
TWO NONCONFORMING QUADRILATERAL ELEMENTS FOR THE REISSNER–MINDLIN PLATE
Mathematical Models and Methods in Applied Sciences, 2005Co-Authors: Pingbing Ming, Zhong-ci ShiAbstract:We construct two low order nonconforming quadrilateral elements for the Reissner–Mindlin plate. The first one consists of a modified nonconforming rotated Q1 element for one component of the rotation and the standard four-node isoparametric element for the other component as well as for the the approximation of the transverse displacement, a modified rotated Raviart–Thomas interpolation Operator is employed as the shear Reduction Operator. The second differs from the first only in the approximation of the rotation, which employs the modified rotated Q1 element for both components of the rotation, and a jump term accounting the discontinuity of the rotation approximation is included in the variational formulation. Both elements give optimal error bounds uniform in the plate thickness with respect to the energy norm as well as the L2 norm.
Luc Waeijen - One of the best experts on this subject based on the ideXlab platform.
-
Reduction Operator for wide simds reconsidered
Design Automation Conference, 2014Co-Authors: Luc Waeijen, Dongrui She, Henk CorporaalAbstract:It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, Reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require Reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs), which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support Reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel Reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% area with a performance penalty of only 6.5%.
-
DAC - Reduction Operator for Wide-SIMDs Reconsidered
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014Co-Authors: Luc Waeijen, Dongrui She, Henk CorporaalAbstract:It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, Reduction is a frequently encountered operation, where multiple input elements need to be combined into a single element by an associative operation, e.g. addition or multiplication. There are many applications that require Reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs), which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support Reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel Reduction algorithms which do not rely on complex communication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better generality, flexibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% area with a performance penalty of only 6.5%.
Wei Chen - One of the best experts on this subject based on the ideXlab platform.
-
A structural rank Reduction Operator for removing artifacts in least-squares reverse time migration
Computers & Geosciences, 2018Co-Authors: Min Bai, Wei ChenAbstract:Abstract Least-square reverse time migration (LSRTM) has been widely accepted because of its exceptional performance in mitigating migration artifacts and preserving the reflection amplitude. Due to the ill-posedness of the inverse problem, regularization methods or constraints must be applied to the reflectivity model. In this paper, we propose a novel iterative LSRTM framework that is regularized by a lowrank constraint. The lowrank constraint is applied along the geological structure of the subsurface reflectivity image and thus can also be called structural lowrank constraint. The lowrank constraint is applied by iteratively applying a rank Reduction Operator that is based on the lowrank approximation theory. The rank Reduction Operator applied along the structure direction can effectively remove those artifacts caused from sparse shot/receiver sampling or other circumstances. Compared with the traditionally used smoothness based constraint, the lowrank constraint is more capable of removing noise while preserving edge details. Since the constraint is applied in post-stack seismic image, the extra computational cost caused by the singular value decomposition (SVD) of the rank Reduction Operator is negligible compared with the computational cost of the migration Operator. Numerical examples with different levels of structural complexity are used to demonstrate the effectiveness and validity of the proposed algorithm.