The Experts below are selected from a list of 24 Experts worldwide ranked by ideXlab platform
C.-p. Chung - One of the best experts on this subject based on the ideXlab platform.
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Code compression by Register Operand dependency
Journal of Systems and Software, 2004Co-Authors: Jyh-jiun J. Shann, C.-p. ChungAbstract:This paper proposes a dictionary-based code compression technique that maps the source Register Operands to the nearest occurrence of a destination Register in the predecessor instructions. The key idea is that most destination Registers have a great possibility to be used as source Registers in the following instructions. The dependent Registers can be removed from the dictionary if this information can be specified otherwise. Such destination source relationships are so common that making use of them can result in much better code compression. After removing the dependent Register Operands, the original dictionary size can be reduced significantly. As a result, the compression ratio can benefit from: (a) the reduction of dictionary size due to the removal of dependent Registers, and (b) the reduction of program encoding due to the reduced number of dictionary entries. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.41% on average for MediaBench benchmarks compiled for MIPS R2000 processor, as opposed to 45% using Operand factorization.
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Interaction between Compilers and Computer Architectures - Code compression by Register Operand dependency
Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures, 2002Co-Authors: Jyh-jiun J. Shann, C.-p. ChungAbstract:This paper proposes a dictionary-based code compression technique that maps the source Register Operands to the nearest occurrence of a destination Register in the predecessor instructions. The key idea is that most destination Registers have great potential to be used as source Registers in the following instructions. The dependent Registers can be removed from the dictionary if this information can be specified otherwise. As a result, the compression ratio benefits from the decreased dictionary size. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.6% on average for MediaBench benchmarks compiled for MIPS R2000 processor.
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Code compression by Register Operand dependency
Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures, 2002Co-Authors: Jyh-jiun J. Shann, C.-p. ChungAbstract:This paper proposes a dictionary-based code compression technique that maps the source Register Operands to the nearest occurrence of a destination Register in the predecessor instructions. The key idea is that most destination Registers have great potential to be used as source Registers in the following instructions. The dependent Registers can be removed from the dictionary if this information can be specified otherwise. As a result, the compression ratio benefits from the decreased dictionary size. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.6% on average for MediaBench benchmarks compiled for MIPS R2000 processor.
Jyh-jiun J. Shann - One of the best experts on this subject based on the ideXlab platform.
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Code compression by Register Operand dependency
Journal of Systems and Software, 2004Co-Authors: Jyh-jiun J. Shann, C.-p. ChungAbstract:This paper proposes a dictionary-based code compression technique that maps the source Register Operands to the nearest occurrence of a destination Register in the predecessor instructions. The key idea is that most destination Registers have a great possibility to be used as source Registers in the following instructions. The dependent Registers can be removed from the dictionary if this information can be specified otherwise. Such destination source relationships are so common that making use of them can result in much better code compression. After removing the dependent Register Operands, the original dictionary size can be reduced significantly. As a result, the compression ratio can benefit from: (a) the reduction of dictionary size due to the removal of dependent Registers, and (b) the reduction of program encoding due to the reduced number of dictionary entries. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.41% on average for MediaBench benchmarks compiled for MIPS R2000 processor, as opposed to 45% using Operand factorization.
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Interaction between Compilers and Computer Architectures - Code compression by Register Operand dependency
Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures, 2002Co-Authors: Jyh-jiun J. Shann, C.-p. ChungAbstract:This paper proposes a dictionary-based code compression technique that maps the source Register Operands to the nearest occurrence of a destination Register in the predecessor instructions. The key idea is that most destination Registers have great potential to be used as source Registers in the following instructions. The dependent Registers can be removed from the dictionary if this information can be specified otherwise. As a result, the compression ratio benefits from the decreased dictionary size. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.6% on average for MediaBench benchmarks compiled for MIPS R2000 processor.
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Code compression by Register Operand dependency
Proceedings Sixth Annual Workshop on Interaction between Compilers and Computer Architectures, 2002Co-Authors: Jyh-jiun J. Shann, C.-p. ChungAbstract:This paper proposes a dictionary-based code compression technique that maps the source Register Operands to the nearest occurrence of a destination Register in the predecessor instructions. The key idea is that most destination Registers have great potential to be used as source Registers in the following instructions. The dependent Registers can be removed from the dictionary if this information can be specified otherwise. As a result, the compression ratio benefits from the decreased dictionary size. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.6% on average for MediaBench benchmarks compiled for MIPS R2000 processor.
Mateo Valero - One of the best experts on this subject based on the ideXlab platform.
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IPDPS - Microarchitectural Support for Speculative Register Renaming
2007 IEEE International Parallel and Distributed Processing Symposium, 2007Co-Authors: Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo ValeroAbstract:This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical Register allocation along with the speculative early release of physical Registers. These renaming policies may cause a Register Operand not to be kept in the physical Register file (PRF). Thus, we add a low-ported auxiliary Register file (XRF) located outside the processor core that keeps the values absent in PRF and supplies them at higher latency. To support the location of Register Operands being either in PRF or XRF, we use virtual Registers. We consider omission and release policies directed by hardware prediction. Namely, we use a single last-use predictor that directs both speculative omission and release. We call this mechanism SR-LUP (speculative renaming based on last-use prediction). Two last-use predictor designs of incremental complexity and performance are analyzed. In a 256-ROB, 8-way processor with an 80int+80fp PRF, SR-LUP with an 11-port 256int+256fp XRF, speeds up computations up to 11.5% and 29% for INT and FP SPEC2K benchmarks, respectively. For FP benchmarks, if the PRF limits the clock frequency, a conventionally managed 128int+128fp PRF can be replaced using SR-LUP by a 64int+64fp PRF backed up with a 10-port 224int+224fp XRF, showing 19% IPS gain.
Jesús Alastruey - One of the best experts on this subject based on the ideXlab platform.
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IPDPS - Microarchitectural Support for Speculative Register Renaming
2007 IEEE International Parallel and Distributed Processing Symposium, 2007Co-Authors: Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo ValeroAbstract:This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical Register allocation along with the speculative early release of physical Registers. These renaming policies may cause a Register Operand not to be kept in the physical Register file (PRF). Thus, we add a low-ported auxiliary Register file (XRF) located outside the processor core that keeps the values absent in PRF and supplies them at higher latency. To support the location of Register Operands being either in PRF or XRF, we use virtual Registers. We consider omission and release policies directed by hardware prediction. Namely, we use a single last-use predictor that directs both speculative omission and release. We call this mechanism SR-LUP (speculative renaming based on last-use prediction). Two last-use predictor designs of incremental complexity and performance are analyzed. In a 256-ROB, 8-way processor with an 80int+80fp PRF, SR-LUP with an 11-port 256int+256fp XRF, speeds up computations up to 11.5% and 29% for INT and FP SPEC2K benchmarks, respectively. For FP benchmarks, if the PRF limits the clock frequency, a conventionally managed 128int+128fp PRF can be replaced using SR-LUP by a 64int+64fp PRF backed up with a 10-port 224int+224fp XRF, showing 19% IPS gain.
Teresa Monreal - One of the best experts on this subject based on the ideXlab platform.
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IPDPS - Microarchitectural Support for Speculative Register Renaming
2007 IEEE International Parallel and Distributed Processing Symposium, 2007Co-Authors: Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo ValeroAbstract:This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical Register allocation along with the speculative early release of physical Registers. These renaming policies may cause a Register Operand not to be kept in the physical Register file (PRF). Thus, we add a low-ported auxiliary Register file (XRF) located outside the processor core that keeps the values absent in PRF and supplies them at higher latency. To support the location of Register Operands being either in PRF or XRF, we use virtual Registers. We consider omission and release policies directed by hardware prediction. Namely, we use a single last-use predictor that directs both speculative omission and release. We call this mechanism SR-LUP (speculative renaming based on last-use prediction). Two last-use predictor designs of incremental complexity and performance are analyzed. In a 256-ROB, 8-way processor with an 80int+80fp PRF, SR-LUP with an 11-port 256int+256fp XRF, speeds up computations up to 11.5% and 29% for INT and FP SPEC2K benchmarks, respectively. For FP benchmarks, if the PRF limits the clock frequency, a conventionally managed 128int+128fp PRF can be replaced using SR-LUP by a 64int+64fp PRF backed up with a 10-port 224int+224fp XRF, showing 19% IPS gain.