The Experts below are selected from a list of 984 Experts worldwide ranked by ideXlab platform
Mateo Valero - One of the best experts on this subject based on the ideXlab platform.
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Microarchitectural Support for Speculative Register Renaming
2007 IEEE International Parallel and Distributed Processing Symposium, 2007Co-Authors: Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo ValeroAbstract:This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative Renaming. We call speculative Renaming to the speculative omission of physical Register allocation along with the speculative early release of physical Registers. These Renaming policies may cause a Register operand not to be kept in the physical Register file (PRF). Thus, we add a low-ported auxiliary Register file (XRF) located outside the processor core that keeps the values absent in PRF and supplies them at higher latency. To support the location of Register operands being either in PRF or XRF, we use virtual Registers. We consider omission and release policies directed by hardware prediction. Namely, we use a single last-use predictor that directs both speculative omission and release. We call this mechanism SR-LUP (speculative Renaming based on last-use prediction). Two last-use predictor designs of incremental complexity and performance are analyzed. In a 256-ROB, 8-way processor with an 80int+80fp PRF, SR-LUP with an 11-port 256int+256fp XRF, speeds up computations up to 11.5% and 29% for INT and FP SPEC2K benchmarks, respectively. For FP benchmarks, if the PRF limits the clock frequency, a conventionally managed 128int+128fp PRF can be replaced using SR-LUP by a 64int+64fp PRF backed up with a 10-port 224int+224fp XRF, showing 19% IPS gain.
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IPDPS - Microarchitectural Support for Speculative Register Renaming
2007 IEEE International Parallel and Distributed Processing Symposium, 2007Co-Authors: Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo ValeroAbstract:This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative Renaming. We call speculative Renaming to the speculative omission of physical Register allocation along with the speculative early release of physical Registers. These Renaming policies may cause a Register operand not to be kept in the physical Register file (PRF). Thus, we add a low-ported auxiliary Register file (XRF) located outside the processor core that keeps the values absent in PRF and supplies them at higher latency. To support the location of Register operands being either in PRF or XRF, we use virtual Registers. We consider omission and release policies directed by hardware prediction. Namely, we use a single last-use predictor that directs both speculative omission and release. We call this mechanism SR-LUP (speculative Renaming based on last-use prediction). Two last-use predictor designs of incremental complexity and performance are analyzed. In a 256-ROB, 8-way processor with an 80int+80fp PRF, SR-LUP with an 11-port 256int+256fp XRF, speeds up computations up to 11.5% and 29% for INT and FP SPEC2K benchmarks, respectively. For FP benchmarks, if the PRF limits the clock frequency, a conventionally managed 128int+128fp PRF can be replaced using SR-LUP by a 64int+64fp PRF backed up with a 10-port 224int+224fp XRF, showing 19% IPS gain.
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dynamic Register Renaming through virtual physical Registers
Journal of Instruction-level Parallelism, 2000Co-Authors: Teresa Monreal, Antonio Gonzalez, Mateo Valero, Jose Antonio Pastor Gonzalez, Víctor ViñalsAbstract:Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic Register Renaming scheme that delays the allocation of physical Registers until a late stage in the pipeline. We show that it can provide important savings in number of physical Registers so it can significantly shorter the Register file access time. Delaying the allocation of physical Registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical Registers, which are tags that do not require any storage location. The proposed Renaming scheme shortens the average number of cycles that each physical Register is allocated, and allows for an early execution of instructions since they can obtain a physical Register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in
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Virtual-Physical Registers
1998Co-Authors: Antonio Gonzalez, José González, Mateo ValeroAbstract:A novel dynamic Register Renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical Registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the Register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical Registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtualphysical Registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a Register to its destination operand. Two alternative allocation strategies have been investigated that differ in the stage where physical Registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed an evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 21 % increase in IPC for a machine with 64 physical Registers in each file) when compared with the traditional Register Renaming approach. 1
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MICRO - Out-of-order vector architectures
Proceedings of 30th Annual International Symposium on Microarchitecture, 1Co-Authors: Roger Espasa, Mateo Valero, James E. SmithAbstract:Register Renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is improved and available memory bandwidth is used more effectively. Using a trace driven simulation we compare a conventional vector implementation, based on the Convex C3400, with an out-of-order, Register Renaming, vector implementation. When the number of physical Registers is above 12, out-of-order execution coupled with Register Renaming provides a speedup of 1.24--1.72 for realistic memory latencies. Out-of-order techniques also tolerate main memory latencies of 100 cycles with a performance degradation less than 6%. The mechanisms used for Register Renaming and out-of-order issue can be used to support precise interrupts -- generally a difficult problem in vector machines. When precise interrupts are implemented, there is typically less than a 10% degradation in performance. A new technique based on Register Renaming is targeted at dynamically eliminating spill code; this technique is shown to provide an extra speedup ranging between 1.10 and 1.20 while reducing total memory traffic by an average of 15--20%.
Antonio Gonzalez - One of the best experts on this subject based on the ideXlab platform.
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HPCA - A Novel Register Renaming Technique for Out-of-Order Processors
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018Co-Authors: Hamid Tabani, Jose-maria Arnau, Jordi Tubella, Antonio GonzalezAbstract:Modern superscalar processors support a large number of in-flight instructions, which requires sizeable Register files. Conventional Register Renaming techniques allocate a new storage location, i.e. physical Register, for every instruction whose destination is a logical Register in order to remove false dependences. Physical Registers are released in a conservative manner when the same logical Register is redefined. For this reason, many cycles may happen between the last read and the release of a physical Register, leading to suboptimal utilization of the Register file. We have observed that for more than 50% of the instructions in SPECfp and more than 30% of the instructions in SPECint that have a destination Register, the produced value has only a single consumer. In this case, the RAW dependence guarantees that the producer-consumer instructions pair will be executed in program order and, hence, the same physical Register can be used to store the value produced by both instructions. In this paper, we propose a Renaming technique that exploits this property to reduce the pressure on the Register file. Our technique leverages physical Register sharing by introducing minor changes in the Register map table and the issue queue. We also describe how our Renaming scheme supports precise exceptions. We evaluated our Renaming technique on top of a modern out-of-order processor. Our experimental results show that it provides 6% speedup on average for the SPEC2006 benchmarks. Alternatively, our Renaming scheme achieves the same performance while reducing the number of physical Registers by 10.5%.
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A Novel Register Renaming Technique for Out-of-Order Processors
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018Co-Authors: Hamid Tabani, Jose-maria Arnau, Jordi Tubella, Antonio GonzalezAbstract:Modern superscalar processors support a large number of in-flight instructions, which requires sizeable Register files. Conventional Register Renaming techniques allocate a new storage location, i.e. physical Register, for every instruction whose destination is a logical Register in order to remove false dependences. Physical Registers are released in a conservative manner when the same logical Register is redefined. For this reason, many cycles may happen between the last read and the release of a physical Register, leading to suboptimal utilization of the Register file. We have observed that for more than 50% of the instructions in SPECfp and more than 30% of the instructions in SPECint that have a destination Register, the produced value has only a single consumer. In this case, the RAW dependence guarantees that the producer-consumer instructions pair will be executed in program order and, hence, the same physical Register can be used to store the value produced by both instructions. In this paper, we propose a Renaming technique that exploits this property to reduce the pressure on the Register file. Our technique leverages physical Register sharing by introducing minor changes in the Register map table and the issue queue. We also describe how our Renaming scheme supports precise exceptions. We evaluated our Renaming technique on top of a modern out-of-order processor. Our experimental results show that it provides 6% speedup on average for the SPEC2006 benchmarks. Alternatively, our Renaming scheme achieves the same performance while reducing the number of physical Registers by 10.5%.
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dynamic Register Renaming through virtual physical Registers
Journal of Instruction-level Parallelism, 2000Co-Authors: Teresa Monreal, Antonio Gonzalez, Mateo Valero, Jose Antonio Pastor Gonzalez, Víctor ViñalsAbstract:Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic Register Renaming scheme that delays the allocation of physical Registers until a late stage in the pipeline. We show that it can provide important savings in number of physical Registers so it can significantly shorter the Register file access time. Delaying the allocation of physical Registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical Registers, which are tags that do not require any storage location. The proposed Renaming scheme shortens the average number of cycles that each physical Register is allocated, and allows for an early execution of instructions since they can obtain a physical Register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in
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Virtual-Physical Registers
1998Co-Authors: Antonio Gonzalez, José González, Mateo ValeroAbstract:A novel dynamic Register Renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical Registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the Register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical Registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtualphysical Registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a Register to its destination operand. Two alternative allocation strategies have been investigated that differ in the stage where physical Registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed an evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 21 % increase in IPC for a machine with 64 physical Registers in each file) when compared with the traditional Register Renaming approach. 1
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HPCA - Virtual-physical Registers
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture, 1Co-Authors: Antonio Gonzalez, José González, Mateo ValeroAbstract:A novel dynamic Register Renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical Registers until a late stage in the pipeline, instead of doing it in the decode stage as conventional schemes do. In this way, the Register pressure is reduced and the processor can exploit more instruction-level parallelism. Delaying the allocation of physical Registers require some additional artifact to keep track of dependences. This is achieved by introducing the concept of virtual-physical Registers, which do not require any storage location and are used to identify dependences among instructions that have not yet allocated a Register to its destination operand. Two alternative allocation strategies have been investigated that differ in the stage where physical Registers are allocated: issue or write-back. The experimental evaluation has confirmed the higher performance of the latter alternative. We have performed all evaluation of the novel scheme through a detailed simulation of a dynamically scheduled processor. The results show a significant improvement (e.g., 19% increase in IPC for a machine with 64 physical Registers in each file) when compared with the traditional Register Renaming approach.
Dongrui Fan - One of the best experts on this subject based on the ideXlab platform.
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Chinese Academy of Sciences
2015Co-Authors: Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui FanAbstract:Register Renaming scheme for stack-base
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optimized Register Renaming scheme for stack based x86 operations
Automation Robotics and Control Systems, 2007Co-Authors: Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui FanAbstract:The stack-based floating point unit (FPU) in the x86 architecture limits its floating point (FP) performance. The flat Register file can improve FP performance but affect x86 compatibility. This paper presents an optimized two-phase floating point Register Renaming scheme used in implementing an x86-compliant processor. The two-phase Renaming scheme eliminates the implicit dependencies between the consecutive FP instructions and redundant operations. As two applications of the method, the techniques used in the second phase of the scheme can eliminate redundant loads and reduce the mis-speculation ratio of the load-store queue. Moreover, the performance of a binary translation system that translates instructions in x86 to MIPS-like ISA can also be boosted by adding the related architectural supports in this optimized scheme to the architecture.
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ARCS - Optimized Register Renaming scheme for stack-based x86 operations
Lecture Notes in Computer Science, 1Co-Authors: Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui FanAbstract:The stack-based floating point unit (FPU) in the x86 architecture limits its floating point (FP) performance. The flat Register file can improve FP performance but affect x86 compatibility. This paper presents an optimized two-phase floating point Register Renaming scheme used in implementing an x86-compliant processor. The two-phase Renaming scheme eliminates the implicit dependencies between the consecutive FP instructions and redundant operations. As two applications of the method, the techniques used in the second phase of the scheme can eliminate redundant loads and reduce the mis-speculation ratio of the load-store queue. Moreover, the performance of a binary translation system that translates instructions in x86 to MIPS-like ISA can also be boosted by adding the related architectural supports in this optimized scheme to the architecture.
Hidetsugu Irie - One of the best experts on this subject based on the ideXlab platform.
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a high performance out of order soft processor without Register Renaming
Field-Programmable Logic and Applications, 2020Co-Authors: Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi SakaiAbstract:Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for high-performance soft processors in FPGAs has increased. The performance of processors is enhanced through out-of-order (OoO) superscalar execution using a Register Renaming mechanism. However, the Register Renaming mechanism has two problems. First, it requires a Register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, Register Renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. These problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without Register Renaming. This approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.
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FPL - A High-Performance Out-of-Order Soft Processor Without Register Renaming
2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020Co-Authors: Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi SakaiAbstract:Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for high-performance soft processors in FPGAs has increased. The performance of processors is enhanced through out-of-order (OoO) superscalar execution using a Register Renaming mechanism. However, the Register Renaming mechanism has two problems. First, it requires a Register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, Register Renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. These problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without Register Renaming. This approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.
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an area efficient out of order soft core processor without Register Renaming
Field-Programmable Technology, 2018Co-Authors: Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Shuichi SakaiAbstract:In this paper, we present an out-of-order soft-core processor adopting STRAIGHT architecture. STRAIGHT has a unique instruction format in which source operands are expressed as distances from producer instructions. This eliminates the need for Register Renaming and eliminates a Register map table (RMT), which usually consists of a large multi-port RAM. That leads to small area, low power consumption, and high scalability of the front-end pipeline width. Moreover, the simplified architecture enables rapid miss-recovery. The prototype is implemented and evaluated on an FPGA. Compared to an out-of-order soft-core processor with a conventional RISC ISA, the proposed soft-core consumes 147-829 fewer LUTs for the front-end pipeline. The evaluation results show that the proposed soft-core is correctly operating on an FPGA, and estimated dynamic power consumption of the soft-core is 0.120 W.
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straight hazardless processor architecture without Register Renaming
International Symposium on Microarchitecture, 2018Co-Authors: Hidetsugu Irie, Toru Koizumi, Ryota Shioya, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Takahiro Notsu, Katsuhiro Yoda, Teruo IshiharaAbstract:The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with Register Renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, Register Renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for Renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors.
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MICRO - STRAIGHT: hazardless processor architecture without Register Renaming
2018 51st Annual IEEE ACM International Symposium on Microarchitecture (MICRO), 2018Co-Authors: Hidetsugu Irie, Toru Koizumi, Ryota Shioya, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Takahiro Notsu, Katsuhiro Yoda, Teruo IshiharaAbstract:The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with Register Renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, Register Renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for Renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors.
Ryota Shioya - One of the best experts on this subject based on the ideXlab platform.
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a high performance out of order soft processor without Register Renaming
Field-Programmable Logic and Applications, 2020Co-Authors: Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi SakaiAbstract:Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for high-performance soft processors in FPGAs has increased. The performance of processors is enhanced through out-of-order (OoO) superscalar execution using a Register Renaming mechanism. However, the Register Renaming mechanism has two problems. First, it requires a Register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, Register Renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. These problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without Register Renaming. This approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.
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FPL - A High-Performance Out-of-Order Soft Processor Without Register Renaming
2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020Co-Authors: Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi SakaiAbstract:Owing to the growth of FPGA-based systems and the increasing complexity of applications, the demand for high-performance soft processors in FPGAs has increased. The performance of processors is enhanced through out-of-order (OoO) superscalar execution using a Register Renaming mechanism. However, the Register Renaming mechanism has two problems. First, it requires a Register mapping table (RMT), which usually comprises a RAM with a large number of ports. A multi-port RAM is not suitable for an FPGA. Second, Register Renaming complicates recovery mechanisms for exceptions, such as branch mispredictions. These problems increase the usage of resources and hinder the improvement of performance. Recently, the STRAIGHT architecture was proposed to solve these problems. STRAIGHT has a unique instruction format and enables OoO execution without Register Renaming. This approach eliminates the RMT and makes the recovery operation more efficient. In this study, we demonstrate a high-performance OoO STRAIGHT soft processor by implementing several mechanisms for adopting the STRAIGHT architecture and fabricate the first STRAIGHT processor capable of executing practical complex programs. Compared to a state-of-the-art OoO soft processor, our processor consumes approximately 17% fewer LUTs and 10% fewer FlipFlops and achieves 15% higher performance in CoreMark, which is a standard benchmark.
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an area efficient out of order soft core processor without Register Renaming
Field-Programmable Technology, 2018Co-Authors: Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Shuichi SakaiAbstract:In this paper, we present an out-of-order soft-core processor adopting STRAIGHT architecture. STRAIGHT has a unique instruction format in which source operands are expressed as distances from producer instructions. This eliminates the need for Register Renaming and eliminates a Register map table (RMT), which usually consists of a large multi-port RAM. That leads to small area, low power consumption, and high scalability of the front-end pipeline width. Moreover, the simplified architecture enables rapid miss-recovery. The prototype is implemented and evaluated on an FPGA. Compared to an out-of-order soft-core processor with a conventional RISC ISA, the proposed soft-core consumes 147-829 fewer LUTs for the front-end pipeline. The evaluation results show that the proposed soft-core is correctly operating on an FPGA, and estimated dynamic power consumption of the soft-core is 0.120 W.
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straight hazardless processor architecture without Register Renaming
International Symposium on Microarchitecture, 2018Co-Authors: Hidetsugu Irie, Toru Koizumi, Ryota Shioya, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Takahiro Notsu, Katsuhiro Yoda, Teruo IshiharaAbstract:The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with Register Renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, Register Renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for Renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors.
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MICRO - STRAIGHT: hazardless processor architecture without Register Renaming
2018 51st Annual IEEE ACM International Symposium on Microarchitecture (MICRO), 2018Co-Authors: Hidetsugu Irie, Toru Koizumi, Ryota Shioya, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Takahiro Notsu, Katsuhiro Yoda, Teruo IshiharaAbstract:The single-thread performance of a processor improves the capability of the entire system by reducing the critical path latency of programs. Typically, conventional superscalar processors improve this performance by introducing out-of-order (OoO) execution with Register Renaming. However, it is also known to increase the complexity and affect the power efficiency. This paper realizes a novel computer architecture called "STRAIGHT" to resolve this dilemma. The key feature is a unique instruction format in which the source operand is given based on the distance from the producer instruction. By leveraging this format, Register Renaming is completely removed from the pipeline. This paper presents the practical Instruction Set Architecture (ISA) design, the novel efficient OoO microarchitecture, and the compilation algorithm for the STRAIGHT machine code. Because the ISA has sequential execution semantics, as in general CPUs, and is provided with a compiler, programming for the architecture is as easy as that of conventional CPUs. A compiler, an assembler, a linker, and a cycle-accurate simulator are developed to measure the performance. Moreover, an RTL description of STRAIGHT is developed to estimate the power reduction. The evaluation using standard benchmarks shows that the performance of STRAIGHT is 18.8% better than the conventional superscalar processor of the same issue-width and instruction window size. This improvement is achieved by STRAIGHT's rapid miss-recovery. Compilation technology for resolving the possible overhead of the ISA is also revealed. The RTL power analysis shows that the architecture reduces the power consumption by removing the power for Renaming. The revealed performance and efficiencies support that STRAIGHT is a novel viable alternative for designing general purpose OoO processors.