The Experts below are selected from a list of 33 Experts worldwide ranked by ideXlab platform
Murali Annavaram - One of the best experts on this subject based on the ideXlab platform.
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improving energy efficiency of gpus through data compression and compressed execution
IEEE Transactions on Computers, 2017Co-Authors: Sangpil Lee, Hyeran Jeon, Keunsoo Kim, Gunjae Koo, Murali AnnavaramAbstract:GPU design trends show that the Register file size will continue to increase to enable even more thread level parallelism. As a Result Register file consumes a large fraction of the total GPU chip power. This paper explores Register file data compression for GPUs to improve power efficiency. Compression reduces the width of the Register file read and write operations, which in turn reduces dynamic power. This work is motivated by the observation that the Register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread Registers is small. Compression exploits the value similarity by removing data redundancy of Register values. Without decompressing operand values some instructions can be processed inside Register file, which enables to further save energy by minimizing data movement and processing in power hungry main execution unit. Evaluation Results show that the proposed techniques save 25 percent of the total Register file energy consumption and 21 percent of the total execution unit energy consumption with negligible performance impact.
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ISCA - Warped-compression: enabling power efficient GPUs through Register compression
Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15, 2015Co-Authors: Hyeran Jeon, Won Woo Ro, Murali AnnavaramAbstract:This paper presents Warped-Compression, a warp-level Register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the Register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread Registers is small. Removing data redundancy of Register values through Register compression reduces the effective Register width, thereby enabling power reduction opportunities. GPU Register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a Result Register file consumes a large fraction of the total GPU chip power. GPU design trends show that the Register file size will continue to increase to enable even more thread level parallelism. To reduce Register file data redundancy warped-compression uses low-cost and implementation-efficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked Register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single Register, or one of the Register banks, as the primary base and then computing delta values of all the other Registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing Register values, each warp-level Register access activates fewer Register banks, which leads to reduction in dynamic power. When fewer banks are used to store the Register content, leakage power can be reduced by power gating the unused banks. Evaluation Results show that Register compression saves 25% of the total Register file power consumption.
Kwang-youb Lee - One of the best experts on this subject based on the ideXlab platform.
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ISCAS (5) - A fast-serial finite field multiplier without increasing the number of Registers
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 1Co-Authors: Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb LeeAbstract:In this paper, an efficient architecture for the finite field multiplier is proposed. As conventional LFSR (Linear Feedback Shift Registers) architecture need as many Registers as speedup factor, the proposed architecture can achieve fast multiplication without increasing the number of Registers by sharing the Result Register for even and odd bits. Modular cells are designed for easy implementation of the multiplier. The experimental Results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier with the same number of Registers. The low power feature of the proposed multiplier has a big advantage for power critical application including smart card cryptography processors.
Hyeran Jeon - One of the best experts on this subject based on the ideXlab platform.
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improving energy efficiency of gpus through data compression and compressed execution
IEEE Transactions on Computers, 2017Co-Authors: Sangpil Lee, Hyeran Jeon, Keunsoo Kim, Gunjae Koo, Murali AnnavaramAbstract:GPU design trends show that the Register file size will continue to increase to enable even more thread level parallelism. As a Result Register file consumes a large fraction of the total GPU chip power. This paper explores Register file data compression for GPUs to improve power efficiency. Compression reduces the width of the Register file read and write operations, which in turn reduces dynamic power. This work is motivated by the observation that the Register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread Registers is small. Compression exploits the value similarity by removing data redundancy of Register values. Without decompressing operand values some instructions can be processed inside Register file, which enables to further save energy by minimizing data movement and processing in power hungry main execution unit. Evaluation Results show that the proposed techniques save 25 percent of the total Register file energy consumption and 21 percent of the total execution unit energy consumption with negligible performance impact.
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ISCA - Warped-compression: enabling power efficient GPUs through Register compression
Proceedings of the 42nd Annual International Symposium on Computer Architecture - ISCA '15, 2015Co-Authors: Hyeran Jeon, Won Woo Ro, Murali AnnavaramAbstract:This paper presents Warped-Compression, a warp-level Register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the Register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread Registers is small. Removing data redundancy of Register values through Register compression reduces the effective Register width, thereby enabling power reduction opportunities. GPU Register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a Result Register file consumes a large fraction of the total GPU chip power. GPU design trends show that the Register file size will continue to increase to enable even more thread level parallelism. To reduce Register file data redundancy warped-compression uses low-cost and implementation-efficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked Register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single Register, or one of the Register banks, as the primary base and then computing delta values of all the other Registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing Register values, each warp-level Register access activates fewer Register banks, which leads to reduction in dynamic power. When fewer banks are used to store the Register content, leakage power can be reduced by power gating the unused banks. Evaluation Results show that Register compression saves 25% of the total Register file power consumption.
Wonjong Kim - One of the best experts on this subject based on the ideXlab platform.
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ISCAS (5) - A fast-serial finite field multiplier without increasing the number of Registers
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 1Co-Authors: Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb LeeAbstract:In this paper, an efficient architecture for the finite field multiplier is proposed. As conventional LFSR (Linear Feedback Shift Registers) architecture need as many Registers as speedup factor, the proposed architecture can achieve fast multiplication without increasing the number of Registers by sharing the Result Register for even and odd bits. Modular cells are designed for easy implementation of the multiplier. The experimental Results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier with the same number of Registers. The low power feature of the proposed multiplier has a big advantage for power critical application including smart card cryptography processors.
J Ferrante - One of the best experts on this subject based on the ideXlab platform.
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CGO - Phi-predication for light-weight if-conversion
International Symposium on Code Generation and Optimization 2003. CGO 2003., 2003Co-Authors: Weihaw Chuang, B. Calder, J FerranteAbstract:Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the Result update is conditional based upon the outcome of the guarding predicate. However, conditional writing of a Register creates a naming problem for an out-of-order processor, and can stall the issuing of instructions. This problem arises from potential multiple predicated definitions reaching a use, which is unresolved until the prior predicate values are computed.In this paper we focus on a light-weight form of predication, Phi-Predication, where all predicated instructions write a Result value to their Register regardless of the predicate value (i.e. even if it is false). Therefore, the predicate does not guard the writing of the Result Register; it instead acts as a form of selection between two input Registers. This eliminates the naming problem for an out-of-order processor. Our Phi-Predicated ISA is derived from the predicated features of the Multiflow ISA, with extensions to efficiently predicate complex control flow. Our compiler modifications also expand upon prior techniques to provide efficient code generation. We examine the use of Phi-Predication for an in-order and out-of-order architecture and compare its performance to using select-op and IA64 ISA predication.