The Experts below are selected from a list of 27 Experts worldwide ranked by ideXlab platform
P. Robinson - One of the best experts on this subject based on the ideXlab platform.
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ICCD - Self calibrating Clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: S.w. Moore, P.a. Cunningham, R.d. Mullins, G. Taylor, P. RobinsonAbstract:We present a local Clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global Clock. After initial tuning, the local Clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these Clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local Clock domain is made possible by stretching the local Clock if a metastable condition could be encountered. Stretching the Clock just requires the Rising Clock Edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the Clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.
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Self calibrating Clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: S.w. Moore, G.s. Taylor, P.a. Cunningham, R.d. Mullins, P. RobinsonAbstract:We present a local Clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global Clock. After initial tuning, the local Clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these Clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local Clock domain is made possible by stretching the local Clock if a metastable condition could be encountered. Stretching the Clock just requires the Rising Clock Edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the Clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.
Ann Gordon-ross - One of the best experts on this subject based on the ideXlab platform.
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ISSoC - A double data rate 8T-cell SRAM architecture for systems-on-chip
2012 International Symposium on System on Chip (SoC), 2012Co-Authors: Saleh M. Abdel-hafeez, Mohammad Shatnawi, Ann Gordon-rossAbstract:The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules (corresponding to even and odd addresses), which are accessed alternatingly. Write accesses occur at both Clock Edges such that the even modules are accessed at the Rising Edge and the odd modules are accessed at the falling Edge. Similarly, the read accesses occur at both Clock Edges such that the even modules are assumed to be evaluated at the Rising Clock Edge, while concurrently the odd modules are pre-charged, and vice versa. We implement a 128-bit × 64-bit SRAM with DDR accesses and an 8T-Cell structure using a standard 0.09µm/1V CMOS TSMC process. Simulation results reveal that our architecture operates with a 1GHz read/write cycle, a data throughput of 2GHz/64-bit, and an average power consumption of 23.4mW.
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A double data rate 8T-cell SRAM architecture for systems-on-chip
2012 International Symposium on System on Chip (SoC), 2012Co-Authors: Saleh M. Abdel-hafeez, Mohammad Shatnawi, Ann Gordon-rossAbstract:The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules (corresponding to even and odd addresses), which are accessed alternatingly. Write accesses occur at both Clock Edges such that the even modules are accessed at the Rising Edge and the odd modules are accessed at the falling Edge. Similarly, the read accesses occur at both Clock Edges such that the even modules are assumed to be evaluated at the Rising Clock Edge, while concurrently the odd modules are pre-charged, and vice versa. We implement a 128-bit × 64-bit SRAM with DDR accesses and an 8T-Cell structure using a standard 0.09μm/1V CMOS TSMC process. Simulation results reveal that our architecture operates with a 1GHz read/write cycle, a data throughput of 2GHz/64-bit, and an average power consumption of 23.4mW.
S.w. Moore - One of the best experts on this subject based on the ideXlab platform.
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ICCD - Self calibrating Clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: S.w. Moore, P.a. Cunningham, R.d. Mullins, G. Taylor, P. RobinsonAbstract:We present a local Clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global Clock. After initial tuning, the local Clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these Clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local Clock domain is made possible by stretching the local Clock if a metastable condition could be encountered. Stretching the Clock just requires the Rising Clock Edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the Clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.
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Self calibrating Clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: S.w. Moore, G.s. Taylor, P.a. Cunningham, R.d. Mullins, P. RobinsonAbstract:We present a local Clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global Clock. After initial tuning, the local Clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these Clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local Clock domain is made possible by stretching the local Clock if a metastable condition could be encountered. Stretching the Clock just requires the Rising Clock Edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the Clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.
Saleh M. Abdel-hafeez - One of the best experts on this subject based on the ideXlab platform.
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ISSoC - A double data rate 8T-cell SRAM architecture for systems-on-chip
2012 International Symposium on System on Chip (SoC), 2012Co-Authors: Saleh M. Abdel-hafeez, Mohammad Shatnawi, Ann Gordon-rossAbstract:The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules (corresponding to even and odd addresses), which are accessed alternatingly. Write accesses occur at both Clock Edges such that the even modules are accessed at the Rising Edge and the odd modules are accessed at the falling Edge. Similarly, the read accesses occur at both Clock Edges such that the even modules are assumed to be evaluated at the Rising Clock Edge, while concurrently the odd modules are pre-charged, and vice versa. We implement a 128-bit × 64-bit SRAM with DDR accesses and an 8T-Cell structure using a standard 0.09µm/1V CMOS TSMC process. Simulation results reveal that our architecture operates with a 1GHz read/write cycle, a data throughput of 2GHz/64-bit, and an average power consumption of 23.4mW.
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A double data rate 8T-cell SRAM architecture for systems-on-chip
2012 International Symposium on System on Chip (SoC), 2012Co-Authors: Saleh M. Abdel-hafeez, Mohammad Shatnawi, Ann Gordon-rossAbstract:The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules (corresponding to even and odd addresses), which are accessed alternatingly. Write accesses occur at both Clock Edges such that the even modules are accessed at the Rising Edge and the odd modules are accessed at the falling Edge. Similarly, the read accesses occur at both Clock Edges such that the even modules are assumed to be evaluated at the Rising Clock Edge, while concurrently the odd modules are pre-charged, and vice versa. We implement a 128-bit × 64-bit SRAM with DDR accesses and an 8T-Cell structure using a standard 0.09μm/1V CMOS TSMC process. Simulation results reveal that our architecture operates with a 1GHz read/write cycle, a data throughput of 2GHz/64-bit, and an average power consumption of 23.4mW.
R.d. Mullins - One of the best experts on this subject based on the ideXlab platform.
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ICCD - Self calibrating Clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: S.w. Moore, P.a. Cunningham, R.d. Mullins, G. Taylor, P. RobinsonAbstract:We present a local Clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global Clock. After initial tuning, the local Clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these Clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local Clock domain is made possible by stretching the local Clock if a metastable condition could be encountered. Stretching the Clock just requires the Rising Clock Edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the Clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.
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Self calibrating Clocks for globally asynchronous locally synchronous systems
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: S.w. Moore, G.s. Taylor, P.a. Cunningham, R.d. Mullins, P. RobinsonAbstract:We present a local Clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global Clock. After initial tuning, the local Clock remains calibrated when environmental conditions change. Each module of a large system on a chip can use one of these Clock generators running at the optimal frequency for the module. Communication between locally synchronous blocks is provided by a globally asynchronous interconnect. Reliable low latency communication between the asynchronous interconnect and a local Clock domain is made possible by stretching the local Clock if a metastable condition could be encountered. Stretching the Clock just requires the Rising Clock Edge to be prevented from entering the tuned delay line. Similarly, a sleep state can be entered by stopping the Clock and wakeup is almost instantaneous. Fine grained sleeping is possible by sleeping whenever there is no work to be undertaken and waking up as soon as new data appears over the asynchronous interconnect.
