The Experts below are selected from a list of 8970 Experts worldwide ranked by ideXlab platform
Kang G Shin - One of the best experts on this subject based on the ideXlab platform.
-
a Router Architecture for real time communication in multicomputer networks
IEEE Transactions on Computers, 1998Co-Authors: Jennifer Rexford, John W Hall, Kang G ShinAbstract:Parallel machines have the potential to satisfy the large computational demands of real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on throughput and latency, while good average performance suffices for best-effort packets. This paper presents a new Router Architecture that tailors low-level routing, switching, arbitration, flow-control, and deadlock-avoidance policies to the conflicting demands of each traffic class. The Router implements bandwidth regulation and deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay and buffer requirements for time-constrained traffic while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the Router includes a novel packet scheduler that shares link-scheduling logic across the multiple output ports, while masking the effects of dock rollover on the representation of packet eligibility times and deadlines. Using the Verilog hardware description language and the Epoch silicon compiler, we demonstrate that the Router design meets the performance goals of both traffic classes in a single-chip solution. Verilog simulation experiments on a detailed timing model of the chip show how the implementation and performance properties of the packet scheduler scale over a range of architectural parameters.
-
a Router Architecture for real time point to point networks
International Symposium on Computer Architecture, 1996Co-Authors: Jennifer Rexford, John W Hall, Kang G ShinAbstract:Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on latency or throughput while good average performance suffices for best-effort packets. This paper presents a Router Architecture that tailors low-level routing, switching, arbitration and flow-control policies to the conflicting demands of each traffic class. The Router implements deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay for time-constrained traffic, while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the Router shares packet buffers and link-scheduling logic between the multiple output ports. Verilog simulations demonstrate that the design meets the performance goals of both traffic classes in a single-chip solution.
A Miliou - One of the best experts on this subject based on the ideXlab platform.
-
a 320 gb s throughput capable 2 times 2 silicon plasmonic Router Architecture for optical interconnects
Journal of Lightwave Technology, 2011Co-Authors: S Papaioannou, K Vyrsokinos, Odysseas Tsilipakos, Alexandros Pitilakis, Karim Hassan, J C Weeber, Laurent Markey, Alain Dereux, Sergey I Bozhevolnyi, A MiliouAbstract:We demonstrate a 2 × 2 silicon-plasmonic Router Architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed Router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The Router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final Router Architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.
S Papaioannou - One of the best experts on this subject based on the ideXlab platform.
-
Silicon-Plasmonic Router Architecture for Optical Interconnects
2016Co-Authors: S Papaioannou, K Vyrsokinos, Odysseas Tsilipakos, Alexandros Pitilakis, Karim Hassan, -c. J. Weeber, Laurent MarkeyAbstract:Abstract—We demonstrate a 2 2 silicon-plasmonic Router ar-chitecture with 320 Gb/s throughput capabilities for optical in-terconnect applications. The proposed Router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multi-plexing and header processing functionalities. We present exper-imental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two race-track resonators of 5.5 m radius and 4 m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experi-mental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 2 thermo
-
a 320 gb s throughput capable 2 times 2 silicon plasmonic Router Architecture for optical interconnects
Journal of Lightwave Technology, 2011Co-Authors: S Papaioannou, K Vyrsokinos, Odysseas Tsilipakos, Alexandros Pitilakis, Karim Hassan, J C Weeber, Laurent Markey, Alain Dereux, Sergey I Bozhevolnyi, A MiliouAbstract:We demonstrate a 2 × 2 silicon-plasmonic Router Architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed Router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The Router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final Router Architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.
Laurent Markey - One of the best experts on this subject based on the ideXlab platform.
-
Silicon-Plasmonic Router Architecture for Optical Interconnects
2016Co-Authors: S Papaioannou, K Vyrsokinos, Odysseas Tsilipakos, Alexandros Pitilakis, Karim Hassan, -c. J. Weeber, Laurent MarkeyAbstract:Abstract—We demonstrate a 2 2 silicon-plasmonic Router ar-chitecture with 320 Gb/s throughput capabilities for optical in-terconnect applications. The proposed Router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multi-plexing and header processing functionalities. We present exper-imental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two race-track resonators of 5.5 m radius and 4 m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experi-mental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 2 thermo
-
a 320 gb s throughput capable 2 times 2 silicon plasmonic Router Architecture for optical interconnects
Journal of Lightwave Technology, 2011Co-Authors: S Papaioannou, K Vyrsokinos, Odysseas Tsilipakos, Alexandros Pitilakis, Karim Hassan, J C Weeber, Laurent Markey, Alain Dereux, Sergey I Bozhevolnyi, A MiliouAbstract:We demonstrate a 2 × 2 silicon-plasmonic Router Architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed Router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The Router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final Router Architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.
Tsutomu Yoshinaga - One of the best experts on this subject based on the ideXlab platform.
-
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
IEEE Transactions on Computers, 2011Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a low-latency Router Architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce communication latency. The packets coming into the prediction Routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing communication latency is the hit rates of the prediction algorithms, which vary based on network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-latency Routers that skip one or more pipeline stages use a bypass data path that is based on a static or single bypassing policy (e.g., accelerating the packets moving in the same dimension), our prediction Router Architecture predictively forwards packets based on the prediction algorithm selected from among several candidates in response to the network environment. We analyze the prediction hit rates of five prediction algorithms on meshes, tori, fat trees, and Spidergons. Then, we present four case studies, each of which assumes different many-core Architectures. We implemented the prediction Routers for each case study by using a 45 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero-load latency, hardware amount, and energy consumption. A typical prediction Router with two or three predictors shows that although the area and energy are increased by 4.8-12.0 percent and 5.3 percent, respectively, up to 89.8 percent of the prediction hit rate is achieved in real applications, which provides favorable trade-offs between modest hardware/energy overheads and significant latency saving.
-
Prediction Router: Yet another low latency on-chip Router Architecture
Proceedings - International Symposium on High-Performance Computer Architecture, 2009Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core Architectures. To reduce the communication latency, we propose a low-latency Router Architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction Routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the communication latency is the hit rates of prediction algorithms, which vary from the network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-latency Routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction Router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core Architecture. We have implemented a prediction Router for each case study by using a 65 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4-15.9% and 8.0-9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the latency saving.
