The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform
Zemin Liu - One of the best experts on this subject based on the ideXlab platform.
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Application of a reduced Hopfield neural net on dynamic Routing in real time communication network
9th International Conference on Artificial Neural Networks: ICANN '99, 1999Co-Authors: Liang Zhang, Zemin LiuAbstract:We propose a virtue token algorithm for finding an optimal route in real time communication network, and use a Hopfield neural net to implement it. Our Hopfield neural net Routing method cannot only satisfy the Routing Requirement of a dynamic communication network, but can also be implemented into hardware. Moreover, our Hopfield neural net can be reduced to a much smaller scale, thus making the hardware implementation applicable.
Jiping Liu - One of the best experts on this subject based on the ideXlab platform.
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Decomposition design theory and methodology for arbitrary-shaped switch boxes
IEEE Transactions on Computers, 2006Co-Authors: Hongbing Fan, Ray C. C. Cheung, Jiping LiuAbstract:We consider the optimal design problem for arbitrary-shaped switch box, (r1...rk) which r, terminals are located on side i for i= 1...k and programmable switches are joining pairs of terminals from different sides. Previous investigations on switch box designs mainly focused on regular switch boxes in which all sides have the same number of terminals. By allowing different numbers of terminals on different sides, irregular switch boxes are more general and flexible for applications such as customized FPGAs and reconfigurable interconnection networks. The optimal switch box design problem is to design a switch box satisfying the given shape and Routing capacity specifications with the minimum number of switches. We present a decomposition design method for a wide range of irregular switch boxes. The main idea of our method is to model a Routing Requirement as a nonnegative integer vector satisfying a system of linear equations and then derive a decomposition theory of Routing Requirements based on the theory of systems of linear Diophantine equations. The decomposition theory makes it possible to construct a large irregular switch box by combining small switch boxes of fixed sizes. Specifically, we can design a family of hyperuniversal (universal) (u-d + c)-SBs with B(h-) switches, where d and c are constant vectors and w is a scalar. We illustrate the design method by designing a class of optimal hyperuniversal irregular 3-sided switch boxes and a class of optimal rectangular universal switch boxes. Experimental results on the rectangular universal switch boxes with the VPR router show that the optimal design of irregular switch boxes does pay off.
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General models and a reduction design technique for FPGA switch box designs
IEEE Transactions on Computers, 2003Co-Authors: Hongbing Fan, Jiping LiuAbstract:An FPGA switch box is said to be hyper-universal if it is detailed-routable for any set of multipin nets specifying a Routing Requirement over the switch box. Comparing with the known "universal switch modules", where only 2-pin nets are considered, the hyper-universal switch box model is more general and powerful. This paper studies the generic problem and proposes a systematic designing methodology for hyper-universal (k, W)-switch boxes, where k is the number of sides and W is the number of terminals on each side. We formulate this hyper-universal (k, W)-switch box design problem as a k-parfite graph design problem and propose an efficient reduction design technique. Applying this technique, we can design hyper-universal (k, W)-switch boxes with low O(W) switches for any fixed k. For illustration, we provide optimum hyper-universal (2, W) and (3, W)-switch boxes and a hyper-universal (4, W)-switch box with switch number quite close to the lower bound 6W, which is used in a well-known commercial design without hyper-universal routability. We also conclude that the proposed reduction method can yield an efficient detailed Routing algorithm for any given Routing Requirement as well.
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ASP-DAC - Combinatorial Routing analysis and design of universal switch blocks
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001Co-Authors: Hongbing Fan, Jiping LiuAbstract:A switch block with k sides and W terminals per side ((k; W)-SB) is said to be universal if every set of 2-pin nets satisfying the dimension constraint is simultaneously routable through the switch block. It has been shown that the universal switch blocks (USB) outperform the XC4000-typed switch blocks in routability. In this paper, we present a new combinatorial model and Routing Requirement decomposition theory for analyzing and designing generalized USB models. As a result, we obtain optimum (k,W)-USBs for kl6 with all W's, k = 7,8 with even W's; and nearly optimum (k,W)-UBSs for k = 7; 8 with odd W's, which is a revised result on the previously published.
Gi-yong Song - One of the best experts on this subject based on the ideXlab platform.
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ASICON - Design and verification of an application-specific PLD using VHDL and SystemVerilog
2011 9th IEEE International Conference on ASIC, 2011Co-Authors: Jae-jin Lee, Gi-yong SongAbstract:This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cell contains another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the Routing Requirement in the PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder. Operations of convolution and FIR filter implemented on the proposed PLD are checked using a SystemVerilog-coded verification platform.
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ASP-DAC - Design of an application-specific PLD architecture
Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005Co-Authors: Jae-jin Lee, Gi-yong SongAbstract:This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cells contain another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the Routing Requirement in a PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder.
Liang Zhang - One of the best experts on this subject based on the ideXlab platform.
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Application of a reduced Hopfield neural net on dynamic Routing in real time communication network
9th International Conference on Artificial Neural Networks: ICANN '99, 1999Co-Authors: Liang Zhang, Zemin LiuAbstract:We propose a virtue token algorithm for finding an optimal route in real time communication network, and use a Hopfield neural net to implement it. Our Hopfield neural net Routing method cannot only satisfy the Routing Requirement of a dynamic communication network, but can also be implemented into hardware. Moreover, our Hopfield neural net can be reduced to a much smaller scale, thus making the hardware implementation applicable.
Xu Jian-bo - One of the best experts on this subject based on the ideXlab platform.
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Research on Routing Protocol for WSANs Based on Multi-actor
Computer Engineering, 2009Co-Authors: Xu Jian-boAbstract:As the present Routing protocols for WSNs is not fit for the Requirement of enery consumption and delay for multi-actors in WSANs applications,the function of J-Sim for WSANs is used to design and implement the Routing protocol BHOER for single-actor-selection model in WSANs.Result of simulation and analysis of performance made for BHOER are given wnich show that BHOER can fit for the Routing Requirement in WSANs.
