The Experts below are selected from a list of 9009 Experts worldwide ranked by ideXlab platform
Philippe Ciblat - One of the best experts on this subject based on the ideXlab platform.
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joint Sampling Clock offset and channel estimation for ofdm signals crame spl acute r rao bound and algorithms
IEEE Transactions on Signal Processing, 2006Co-Authors: S. Gault, Walid Hachem, Philippe CiblatAbstract:This paper considers the problem of Sampling Clock synchronization and channel estimation for orthogonal-frequency-division multiplex (OFDM) systems. In such systems, when the number of subcarriers is large, a Sampling Clock frequency mismatch between the transmitter and the receiver dramatically degrades the performance. So far, the literature proposes ad hoc estimation algorithms. However, a complete performance analysis, especially the Crame/spl acute/r-Rao bound (CRB) derivation, remains to be done. Obviously, the channel-impulse response is unknown at the receiver and also needs to be estimated. Therefore, the CRB associated with this joint estimation is theoretically evaluated. When the number of subcarriers and the channel degree are large, very compact closed-form expressions for the CRB are obtained. Furthermore, along with the maximum-likelihood (ML) estimator, suboptimal estimation algorithms are introduced and compared with some existing approaches and with the CRB.
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Joint Sampling Clock offset and channel estimation for OFDM signals: Crame/spl acute/r-Rao bound and algorithms
IEEE Transactions on Signal Processing, 2006Co-Authors: S. Gault, Walid Hachem, Philippe CiblatAbstract:This paper considers the problem of Sampling Clock synchronization and channel estimation for orthogonal-frequency-division multiplex (OFDM) systems. In such systems, when the number of subcarriers is large, a Sampling Clock frequency mismatch between the transmitter and the receiver dramatically degrades the performance. So far, the literature proposes ad hoc estimation algorithms. However, a complete performance analysis, especially the Crame/spl acute/r-Rao bound (CRB) derivation, remains to be done. Obviously, the channel-impulse response is unknown at the receiver and also needs to be estimated. Therefore, the CRB associated with this joint estimation is theoretically evaluated. When the number of subcarriers and the channel degree are large, very compact closed-form expressions for the CRB are obtained. Furthermore, along with the maximum-likelihood (ML) estimator, suboptimal estimation algorithms are introduced and compared with some existing approaches and with the CRB.
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ICASSP (4) - Cramer-Rao bounds for data-aided Sampling Clock offset and channel estimation
2004 IEEE International Conference on Acoustics Speech and Signal Processing, 1Co-Authors: S. Gault, W. Hachem, Philippe CiblatAbstract:We derive the Cramer-Rao bound (CRB) on the joint estimates of the Sampling Clock offset and the channel impulse response when a training sequence is available. Simple closed form expressions are obtained for the CRB in the case where the observation window is large, and furthermore in the case where the channel degree is large. Our derivations are suited for single-carrier as well as for multi-carrier orthogonal frequency division multiplexing (OFDM) schemes. Data-aided maximum-likelihood (ML) estimates are also carried out.
Chen Chu - One of the best experts on this subject based on the ideXlab platform.
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Sampling Clock Synchronization Algorithm with Spatial Diversity in MIMO-OFDM Systems
Computer Simulation, 2009Co-Authors: Chen ChuAbstract:Sampling Clock synchronization is the crucial technique in MIMO-OFDM systems.The spatial diversity algorithm of Sampling offset estimator for MIMO-OFDM systems is proposed.In addition,a lower complexity Sampling Clock recovery design is proposed.The simulation results show that the performance of the proposed algorithm is perfect in fast time-varying frequency-selective fading channels and superior to other algorithms.
Zhigang Cao - One of the best experts on this subject based on the ideXlab platform.
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an improved combined symbol and Sampling Clock synchronization method for ofdm systems
Wireless Communications and Networking Conference, 1999Co-Authors: Baoguo Yang, K B Letaief, R S Cheng, Zhigang CaoAbstract:In this paper, we present a delay-locked loop (DLL) technique for performing a combined symbol and Sampling Clock synchronization in orthogonal frequency division multiplexing (OFDM) systems. In addition, we propose a symbol timing acquisition algorithm for the DLL. It is shown that by using this combined scheme, we can achieve symbol timing recovery and Sampling Clock adjustment simultaneously. In particular, the symbol timing estimation error variance can be decreased by several orders of magnitude compared with the common correlation methods in both the AWGN and multipath fading channels.
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WCNC - An improved combined symbol and Sampling Clock synchronization method for OFDM systems
WCNC. 1999 IEEE Wireless Communications and Networking Conference (Cat. No.99TH8466), 1Co-Authors: Baoguo Yang, K B Letaief, R S Cheng, Zhigang CaoAbstract:In this paper, we present a delay-locked loop (DLL) technique for performing a combined symbol and Sampling Clock synchronization in orthogonal frequency division multiplexing (OFDM) systems. In addition, we propose a symbol timing acquisition algorithm for the DLL. It is shown that by using this combined scheme, we can achieve symbol timing recovery and Sampling Clock adjustment simultaneously. In particular, the symbol timing estimation error variance can be decreased by several orders of magnitude compared with the common correlation methods in both the AWGN and multipath fading channels.
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ML-oriented DA Sampling Clock synchronization for OFDM systems
WCC 2000 - ICCT 2000. 2000 International Conference on Communication Technology Proceedings (Cat. No.00EX420), 1Co-Authors: Baoguo Yang, Zhigang CaoAbstract:The paper describes an error feedback loop for performing the data-aided (DA) Sampling Clock synchronization in orthogonal frequency division multiplexing (OFDM) systems. The algorithm is derived from the joint maximum likelihood (ML) estimation of the sample timing and the carrier phase in the AWGN channel. It is shown that the sample timing estimation variance of the proposed algorithm is asymptotically equal to the Cramer-Rao bound (CRB).
Yun Chiu - One of the best experts on this subject based on the ideXlab platform.
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Calibration of Sampling Clock skew in SHA-less pipeline ADCs
Electronics Letters, 2008Co-Authors: P. Huang, Yun ChiuAbstract:A gradient-based algorithm to adaptively calibrate Sampling Clock skew in sample-and-hold amplifier (SHA)-less pipeline analogue-to-digital converters (ADCs) is presented. It follows that the power consumption of pipeline ADCs can be substantially reduced at the architecture level by employing the SHA-less multi-bit-per-stage architecture and remedying the resulting Sampling Clock skew problem with calibration.
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a gradient based algorithm for Sampling Clock skew calibration of sha less pipeline adcs
International Symposium on Circuits and Systems, 2007Co-Authors: P. Huang, Yun ChiuAbstract:This paper presents a gradient-based algorithm for the Sampling Clock skew calibration of SHA-less pipeline analog-to-digital converters (ADCs). Based on the skew information collected from the output residues of the first pipeline stage, the Clock of the sub-ADC is adaptively adjusted to synchronize with that of the sample-and-hold (S/H) in the first pipeline stage. This Clock skew calibration technique essentially improves the viability of the SHA-less architecture for pipeline ADCs at high input frequencies. It follows that the power consumption of pipeline ADCs can be substantially reduced by eliminating the dedicated, power-hungry front-end sample-and-hold amplifier (SHA) and remedying the resulting Sampling Clock skew problem by adaptive calibration.
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ISCAS - A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: P. Huang, Yun ChiuAbstract:This paper presents a gradient-based algorithm for the Sampling Clock skew calibration of SHA-less pipeline analog-to-digital converters (ADCs). Based on the skew information collected from the output residues of the first pipeline stage, the Clock of the sub-ADC is adaptively adjusted to synchronize with that of the sample-and-hold (S/H) in the first pipeline stage. This Clock skew calibration technique essentially improves the viability of the SHA-less architecture for pipeline ADCs at high input frequencies. It follows that the power consumption of pipeline ADCs can be substantially reduced by eliminating the dedicated, power-hungry front-end sample-and-hold amplifier (SHA) and remedying the resulting Sampling Clock skew problem by adaptive calibration.
Baoguo Yang - One of the best experts on this subject based on the ideXlab platform.
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an improved combined symbol and Sampling Clock synchronization method for ofdm systems
Wireless Communications and Networking Conference, 1999Co-Authors: Baoguo Yang, K B Letaief, R S Cheng, Zhigang CaoAbstract:In this paper, we present a delay-locked loop (DLL) technique for performing a combined symbol and Sampling Clock synchronization in orthogonal frequency division multiplexing (OFDM) systems. In addition, we propose a symbol timing acquisition algorithm for the DLL. It is shown that by using this combined scheme, we can achieve symbol timing recovery and Sampling Clock adjustment simultaneously. In particular, the symbol timing estimation error variance can be decreased by several orders of magnitude compared with the common correlation methods in both the AWGN and multipath fading channels.
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WCNC - An improved combined symbol and Sampling Clock synchronization method for OFDM systems
WCNC. 1999 IEEE Wireless Communications and Networking Conference (Cat. No.99TH8466), 1Co-Authors: Baoguo Yang, K B Letaief, R S Cheng, Zhigang CaoAbstract:In this paper, we present a delay-locked loop (DLL) technique for performing a combined symbol and Sampling Clock synchronization in orthogonal frequency division multiplexing (OFDM) systems. In addition, we propose a symbol timing acquisition algorithm for the DLL. It is shown that by using this combined scheme, we can achieve symbol timing recovery and Sampling Clock adjustment simultaneously. In particular, the symbol timing estimation error variance can be decreased by several orders of magnitude compared with the common correlation methods in both the AWGN and multipath fading channels.
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ML-oriented DA Sampling Clock synchronization for OFDM systems
WCC 2000 - ICCT 2000. 2000 International Conference on Communication Technology Proceedings (Cat. No.00EX420), 1Co-Authors: Baoguo Yang, Zhigang CaoAbstract:The paper describes an error feedback loop for performing the data-aided (DA) Sampling Clock synchronization in orthogonal frequency division multiplexing (OFDM) systems. The algorithm is derived from the joint maximum likelihood (ML) estimation of the sample timing and the carrier phase in the AWGN channel. It is shown that the sample timing estimation variance of the proposed algorithm is asymptotically equal to the Cramer-Rao bound (CRB).
