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M Dubois - One of the best experts on this subject based on the ideXlab platform.

  • cost sensitive Cache replacement algorithms
    High-Performance Computer Architecture, 2003
    Co-Authors: J Jeong, M Dubois
    Abstract:

    Cache replacement algorithms originally developed in the context of simple uniprocessor systems aim to reduce the miss count. However, in modern systems, Cache misses have different costs. The cost may be latency, penalty, power consumption, bandwidth consumption, or any other ad-hoc numerical property attached to a miss. In many practical situations, it is desirable to inject the cost of a miss into the replacement policy. In this paper, we propose several extensions of LRU which account for nonuniform miss costs. These LRU extensions have simple implementations, yet they are very effective in various situations. We first explore the simple case of two static miss costs using trace-driven simulations to understand when cost-sensitive replacements are effective. We show that very large improvements of the cost function are possible in many practical cases. As an example of their effectiveness, we apply the algorithms to the Second-Level Cache of a multiprocessor with superscalar processors, using the miss latency as the cost function. By applying our simple replacement policies sensitive to the latency of misses we can improve the execution time of some parallel applications by up to 18%.

  • hybrid compiler hardware prefetching for multiprocessors using low overhead Cache miss traps
    International Conference on Parallel Processing, 1997
    Co-Authors: J Skeppstedt, M Dubois
    Abstract:

    We propose and evaluate a new data prefetching technique for Cache coherent multiprocessors. Prefetches are issued by a prefetch engine which is controlled by the compiler. Second-Level Cache misses generate Cache miss traps, and start the prefetch engine in a trap handler generated by the compiler. The only instruction overhead in our approach is when a trap handler terminates after data arrives. We present the functionality of the prefetch engine and a compiler algorithm to control it. We also study emulation of the prefetch engine in software. Our techniques are evaluated on six parallel applications using a compiler which incorporates our algorithm and a simulated multiprocessor. The prefetch engines remove up to 67% of the memory access stall time at an instruction overhead less than 0.42%. The emulated prefetch engines remove in general less stall time at a higher instruction overhead.

  • Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-Overhead Cache Miss Traps
    1997
    Co-Authors: J Skeppstedt, M Dubois
    Abstract:

    We propose and evaluate a new data prefetching technique for Cache coherent multiprocessors. Prefetches are issued by a prefetch engine which is controlled by the compiler. Second-Level Cache misses generate Cache miss traps, and start the prefetch engine in a trap handler generated by the compiler. The only instruction overhead in our approach is when a trap handler terminates after data arrives. We present the functionality of the prefetch engine and a compiler algorithm to control it. We also study emulation of the prefetch engine in software. Our techniques are evaluated on six parallel applications using a compiler which incorporates our algorithm anda simulated multiprocessor. The prefetch engines remove up to 67% of the memory access stall time at an instruction overhead less than 0.42%. The emulated prefetch engines remove in general less stall time at a higher instruction overhead. 1 Introduction Data prefetching is a promising approach to hide memory access latencies in cac..

  • implementation and evaluation of update based Cache protocols under relaxed memory consistency models
    Future Generation Computer Systems, 1995
    Co-Authors: Hakan Grahn, Per Stenstrom, M Dubois
    Abstract:

    Abstract Invalidation-based Cache coherence protocols have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas Cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. The purpose of this paper is to compare update- and invalidation-based protocols for their ability to reduce or hide memory access latencies and for their ease of implementation under relaxed memory consistency models. Based on a detailed simulation study, we find that write-update protocols augmented with simple competitive mechanisms — we call such protocols competitive-update protocols — can hide all the write latency and cut the read penalty by as much as 46% at the cost of some increase in the memory traffic. However, as compared to write-invalidate, update-based protocols require more aggressive memory consistency models and more local buffering in the Second-Level Cache to be effective. In addition, their increased number of global writes may cause increased synchronization overhead in applications with high contention for critical sections.

J Skeppstedt - One of the best experts on this subject based on the ideXlab platform.

  • hybrid compiler hardware prefetching for multiprocessors using low overhead Cache miss traps
    International Conference on Parallel Processing, 1997
    Co-Authors: J Skeppstedt, M Dubois
    Abstract:

    We propose and evaluate a new data prefetching technique for Cache coherent multiprocessors. Prefetches are issued by a prefetch engine which is controlled by the compiler. Second-Level Cache misses generate Cache miss traps, and start the prefetch engine in a trap handler generated by the compiler. The only instruction overhead in our approach is when a trap handler terminates after data arrives. We present the functionality of the prefetch engine and a compiler algorithm to control it. We also study emulation of the prefetch engine in software. Our techniques are evaluated on six parallel applications using a compiler which incorporates our algorithm and a simulated multiprocessor. The prefetch engines remove up to 67% of the memory access stall time at an instruction overhead less than 0.42%. The emulated prefetch engines remove in general less stall time at a higher instruction overhead.

  • Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-Overhead Cache Miss Traps
    1997
    Co-Authors: J Skeppstedt, M Dubois
    Abstract:

    We propose and evaluate a new data prefetching technique for Cache coherent multiprocessors. Prefetches are issued by a prefetch engine which is controlled by the compiler. Second-Level Cache misses generate Cache miss traps, and start the prefetch engine in a trap handler generated by the compiler. The only instruction overhead in our approach is when a trap handler terminates after data arrives. We present the functionality of the prefetch engine and a compiler algorithm to control it. We also study emulation of the prefetch engine in software. Our techniques are evaluated on six parallel applications using a compiler which incorporates our algorithm anda simulated multiprocessor. The prefetch engines remove up to 67% of the memory access stall time at an instruction overhead less than 0.42%. The emulated prefetch engines remove in general less stall time at a higher instruction overhead. 1 Introduction Data prefetching is a promising approach to hide memory access latencies in cac..

Alan Jay Smith - One of the best experts on this subject based on the ideXlab platform.

  • the pool of subsectors Cache design
    International Conference on Supercomputing, 1999
    Co-Authors: Jeffrey B Rothman, Alan Jay Smith
    Abstract:

    Sector Caches use an address tag to identify a sector, and valid bits to indicate whether each subsector is present in the Cache. This design permits a small number of tag bits to control a large number of data bytes in the Cache. Such a design is useful for single level Caches when Cache sizes are small and/or when the optimal line sizes are small. Sector Caches are most useful when small first-level tag arrays are used to control large second level Cache data arrays. The problem with sector Caches is that because of the constrained mapping between address tags and data array space, frequently many of the subsectors are not filled before the sector is replaced. In this paper, we propose a new design, called the "sector pool Cache," in which subsectors may be shared between sectors, so that the Cache data arrays are used much more efficiently. We evaluate this design using a large multiprogrammed workload to provide a more realistic test of the various Cache designs. Our results show that the sector pool Cache can be an attractive solution for a first level on-chip Cache when used in conjunction with a regular second level off-chip sector Cache. Such a design provides improved performance by allowing a larger fraction of first level Cache bits to be used for data rather than for tags.

Jeffrey B Rothman - One of the best experts on this subject based on the ideXlab platform.

  • the pool of subsectors Cache design
    International Conference on Supercomputing, 1999
    Co-Authors: Jeffrey B Rothman, Alan Jay Smith
    Abstract:

    Sector Caches use an address tag to identify a sector, and valid bits to indicate whether each subsector is present in the Cache. This design permits a small number of tag bits to control a large number of data bytes in the Cache. Such a design is useful for single level Caches when Cache sizes are small and/or when the optimal line sizes are small. Sector Caches are most useful when small first-level tag arrays are used to control large second level Cache data arrays. The problem with sector Caches is that because of the constrained mapping between address tags and data array space, frequently many of the subsectors are not filled before the sector is replaced. In this paper, we propose a new design, called the "sector pool Cache," in which subsectors may be shared between sectors, so that the Cache data arrays are used much more efficiently. We evaluate this design using a large multiprogrammed workload to provide a more realistic test of the various Cache designs. Our results show that the sector pool Cache can be an attractive solution for a first level on-chip Cache when used in conjunction with a regular second level off-chip sector Cache. Such a design provides improved performance by allowing a larger fraction of first level Cache bits to be used for data rather than for tags.

Joel M Tendler - One of the best experts on this subject based on the ideXlab platform.

  • FEATURING SINGLE-AND MULTITHREADED EXECUTION, THE POWER5 PROVIDES HIGHER PERFORMANCE IN THE SINGLE-THREADED MODE THAN ITS POWER4 PREDECESSOR AT EQUIVALENT FREQUENCIES. ENHANCEMENTS IBM POWER5 CHIP: A DUAL-CORE MULTITHREADED PROCESSOR
    2020
    Co-Authors: Ron Kalla, Balaram Sinharoy, Joel M Tendler
    Abstract:

    IBM introduced Power4-based systems in 2001. 1 The Power4 design integrates two processor cores on a single chip, a shared Second-Level Cache, a directory for an off-chip third-level Cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level. Additionally, the Power4's out-of-order execution design lets the hardware bypass instructions whose operands are not yet available (perhaps because of an earlier Cache miss during register loading) and execute other instructions whose operands are ready. Later, when the operands become available, the hardware can execute the skipped instruction. Coupled with a superscalar design, out-of-order execution results in higher instruction execution parallelism than otherwise possible. The Power5 is the next-generation chip in this line. One of our key goals in designing the Power5 was to maintain both binary and structural compatibility with existing Power4 systems to ensure that binaries continue executing properly and all application optimizations carry forward to newer systems. With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels. In this article, we describe the approach we used to improve chip-level performance. Multithreading Conventional processors execute instructions from a single instruction stream. Despite microarchitectural advances, execution unit utilization remains low in today's microprocessors. It is not unusual to see average execution unit utilization rates of approximately 25 percent across a broad spectrum of environments. To increase execution unit utilization, designers use thread-level parallelism, in which the physical processor core executes instructions from more than one instruction stream. To the operating system, the physical processor core appears as if it is a symmetric multiprocessor containing two logical processors. There are at least three different methods for handling multiple threads. In coarse-grained multithreading, only on

  • ibm power5 chip a dual core multithreaded processor
    IEEE Micro, 2004
    Co-Authors: Ronald Nick Kalla, Balaram Sinharoy, Joel M Tendler
    Abstract:

    IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared Second-Level Cache, a directory for an off-chip third-level Cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level. The Power5 is the next-generation chip in this line. One of our key goals in designing the Power5 was to maintain both binary and structural compatibility with existing Power4 systems to ensure that binaries continue executing properly and all application optimizations carry forward to newer systems. With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels. We describe the approach we used to improve chip-level performance.