The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Tianzhou Chen - One of the best experts on this subject based on the ideXlab platform.
-
Global register alias table: Boosting Sequential Program on multi-core
Future Generation Computer Systems, 2012Co-Authors: Chunhao Wang, Tianzhou ChenAbstract:Executing Sequential Program on multi-core is crucial for accommodating Instruction Level Parallelism (ILP) in Chip Multi-Processor (CMP) architecture. One widely used method for steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings about much hardware complexity and die area overhead. This paper presents the Global Register Alias Table (GRAT), a structure which can be used in CMP architecture to facilitate Sequential Program execution across cores. The GRAT drastically reduces the area overhead and design complexity of steering instructions without introducing additional Programming effort or compiler support. Dynamic reconfiguration is also implemented to support efficient parallel Program execution. In our evaluation, the result shows that our work performs within 5.9% of Core Fusion, a recent work which requires a complex steering unit.
-
CIT - Global Register Alias Table: Executing Sequential Program on Multi-Core
2010 10th IEEE International Conference on Computer and Information Technology, 2010Co-Authors: Chunhao Wang, Lingxiang Xiang, Tianzhou ChenAbstract:Executing Sequential Program on multi-core is crucial for accommodating instruction level parallelism (ILP) in chip multiprocessor (CMP) architecture. One widely used method of steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings much hardware complexity and area overhead. This paper presents the Global Register Alias Table (GRAT), a structure which can be used in CMP architecture to facilitate Sequential Program execution across cores. The GRAT also reduces the area and complexity for steering instructions greatly without introducing additional Programming effort and compiler support. In our evaluation, the result shows that our work performs within 5.9% of Core Fusion, a recent proposal which requires a complex steering unit.
Kenneth Skovhede - One of the best experts on this subject based on the ideXlab platform.
-
building fpga state machines from Sequential code
Field Programmable Gate Arrays, 2019Co-Authors: Carljohannes Johnsen, Kenneth SkovhedeAbstract:State machines are commonly used and well understood for hardware. However, in some cases they can introduce complexity as the Program can no longer be read Sequentially. We propose an extension to the SME model, which retains the Sequential Program structure, by using a barrier-like 'await' construct to divide a Program into states. This is done by awaiting a predicate, ensuring that the Sequential Program does not progress until the predicate is satisfied. This initial implementation enables the clock signal as a predicate, allowing for easy partitioning of the Sequential Program, which is a common approach when either pipelining or sequencing a problem. Future implementations will also enable functions or signal values as predicates. The signal values will be a simple to use barrier when waiting for external input. As for the functions, it handles all the communication regarding input/output for and synchronization with the function. As always with the SME model, the problems implemented in the model can be transpiled into VHDL along with a VHDL test bench, which verifies that the generated VHDL matches the SME simulation. Our preliminary results shows that Xilinx Vivado recognises the state machines and that the SME simulation is clock cycle accurate to the simulation of the generated VHDL. Furthermore, we see reduced resource consumption and higher clock rates, as we should by leveraging state machines, without increasing the complexity and readability of the original Program.
-
FPGA - Building FPGA State Machines from Sequential Code
Proceedings of the 2019 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2019Co-Authors: Carljohannes Johnsen, Kenneth SkovhedeAbstract:State machines are commonly used and well understood for hardware. However, in some cases they can introduce complexity as the Program can no longer be read Sequentially. We propose an extension to the SME model, which retains the Sequential Program structure, by using a barrier-like 'await' construct to divide a Program into states. This is done by awaiting a predicate, ensuring that the Sequential Program does not progress until the predicate is satisfied. This initial implementation enables the clock signal as a predicate, allowing for easy partitioning of the Sequential Program, which is a common approach when either pipelining or sequencing a problem. Future implementations will also enable functions or signal values as predicates. The signal values will be a simple to use barrier when waiting for external input. As for the functions, it handles all the communication regarding input/output for and synchronization with the function. As always with the SME model, the problems implemented in the model can be transpiled into VHDL along with a VHDL test bench, which verifies that the generated VHDL matches the SME simulation. Our preliminary results shows that Xilinx Vivado recognises the state machines and that the SME simulation is clock cycle accurate to the simulation of the generated VHDL. Furthermore, we see reduced resource consumption and higher clock rates, as we should by leveraging state machines, without increasing the complexity and readability of the original Program.
Chunhao Wang - One of the best experts on this subject based on the ideXlab platform.
-
Global register alias table: Boosting Sequential Program on multi-core
Future Generation Computer Systems, 2012Co-Authors: Chunhao Wang, Tianzhou ChenAbstract:Executing Sequential Program on multi-core is crucial for accommodating Instruction Level Parallelism (ILP) in Chip Multi-Processor (CMP) architecture. One widely used method for steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings about much hardware complexity and die area overhead. This paper presents the Global Register Alias Table (GRAT), a structure which can be used in CMP architecture to facilitate Sequential Program execution across cores. The GRAT drastically reduces the area overhead and design complexity of steering instructions without introducing additional Programming effort or compiler support. Dynamic reconfiguration is also implemented to support efficient parallel Program execution. In our evaluation, the result shows that our work performs within 5.9% of Core Fusion, a recent work which requires a complex steering unit.
-
CIT - Global Register Alias Table: Executing Sequential Program on Multi-Core
2010 10th IEEE International Conference on Computer and Information Technology, 2010Co-Authors: Chunhao Wang, Lingxiang Xiang, Tianzhou ChenAbstract:Executing Sequential Program on multi-core is crucial for accommodating instruction level parallelism (ILP) in chip multiprocessor (CMP) architecture. One widely used method of steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings much hardware complexity and area overhead. This paper presents the Global Register Alias Table (GRAT), a structure which can be used in CMP architecture to facilitate Sequential Program execution across cores. The GRAT also reduces the area and complexity for steering instructions greatly without introducing additional Programming effort and compiler support. In our evaluation, the result shows that our work performs within 5.9% of Core Fusion, a recent proposal which requires a complex steering unit.
Andrzej Daniluk - One of the best experts on this subject based on the ideXlab platform.
-
multithreaded transactions in scientific computing the growth06_v2 Program
Computer Physics Communications, 2009Co-Authors: Andrzej DanilukAbstract:Writing a concurrent Program can be more difficult than writing a Sequential Program. Programmer needs to think about synchronization, race conditions and shared variables. Transactions help reduce the inconvenience of using threads. A transaction is an abstraction, which allows Programmers to group a sequence of actions on the Program into a logical, higher-level computation unit. This paper presents a new version of the GROWTHGr and GROWTH06 Programs.
-
multithreaded transactions in scientific computing new versions of a computer Program for kinematical calculations of rheed intensity oscillations
Computer Physics Communications, 2006Co-Authors: Marcin Brzuszek, Andrzej DanilukAbstract:Writing a concurrent Program can be more difficult than writing a Sequential Program. Programmer needs to think about synchronisation, race conditions and shared variables. Transactions help reduce the inconvenience of using threads. A transaction is an abstraction, which allows Programmers to group a sequence of actions on the Program into a logical, higher-level computation unit. This paper presents multithreaded versions of the GROWTH Program, which allow to calculate the layer coverages during the growth of thin epitaxial films and the corresponding RHEED intensities according to the kinematical approximation. The presented Programs also contain graphical user interfaces, which enable displaying Program data at run-time.
Christophe Cérin - One of the best experts on this subject based on the ideXlab platform.
-
Parallelization of Littlewood-Richardson Coefficients Computation and its Integration into the BonjourGrid Meta-Desktop Grid Middleware
International Journal of Grid and High Performance Computing, 2011Co-Authors: Heithem Abbes, Franck Butelle, Christophe CérinAbstract:The aim of this paper is to show how to parallelize a compute intensive application in mathematics (Group Theory) for an institutional Desktop Grid platform coordinated by a meta-grid middleware named BonjourGrid. The paper is twofold: first of all, it shows how to parallelize a Sequential Program for a multicore CPU which participates in the computation and second it demonstrates the effort for launching multiple instances of the solutions for the mathematical problem with the BonjourGrid middleware. BonjourGrid is a fully decentralized Desktop Grid middleware. The main results of the paper are: a) an efficient multi-threaded version of a Sequential Program to compute Littlewood- Richardson coefficients, namely the Multi-LR Program and b) a proof of concept, centered around the user needs, for the BonjourGrid middleware dedicated to coordinate multiple instances of Programsfor Desktop Grids and with the help of Multi-LR. In this paper, the scientific work consists in starting from a model for the solution of a compute intensive problem in mathematics, to incorporate the concrete model into a middleware and running it on commodity PCs platform managed by an innovative meta Desktop Grid middleware.
-
Multithreading of Kostka Numbers Computation for the BonjourGrid Meta-desktop Grid Middleware
2010Co-Authors: Heithem Abbes, Franck Butelle, Christophe CérinAbstract:The aim of this paper is to show how to multithread a compute intensive application in mathematics (Group Theory) for an institutional Desktop Grid platform coordinated by a meta-grid middleware named BonjourGrid which is a fully decentralized Desktop Grid middleware. The paper is twofold: first of all, it shows how to multithread a Sequential Program for a multicore CPU which participates in the computation of some parameters and second it demonstrates the effort for coordinating multiple instances of the BonjourGrid middleware. The main results of the paper are: a) we develop an efficient multi-threaded version of a Sequential Program to compute Kostka numbers, namely the Multi-kostka Program and b) a proof of concept is given, centered on user needs, for the incorporation into the BonjourGrid middleware of Multi-kostka Program.
