The Experts below are selected from a list of 9210 Experts worldwide ranked by ideXlab platform
Eun Jung Kim - One of the best experts on this subject based on the ideXlab platform.
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Fast Secure Communications in Shared Memory Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems, 2011Co-Authors: Manhee Lee, Minseon Ahn, Eun Jung KimAbstract:Protection and security are becoming essential requirements in commercial servers. To provide secure Memory and cache-to-cache communications, we presented Interconnect-Independent Security Enhanced Shared Memory Multiprocessor System (I2SEMS), mainly focusing on how to manage a global counter to encrypt, decrypt, and authenticate data messages with little performance overhead. However, I2SEMS was vulnerable to replay attacks on data messages and integrity attacks on control and counter messages. This paper proposes three authentication schemes to remove those security vulnerabilities. First, we prevent replay attacks on data messages by inserting Request Counter (RC) into request messages. Second, we also use RC to detect integrity attacks on control messages. Third, we propose a new counter, referred to as GCC Counter (GC), to protect the global counter messages. We simulated our design with SPLASH-2 benchmarks on up to 16-processor Shared Memory Multiprocessor systems by using Simics with Wisconsin multifacet General Execution-driven Multiprocessor Simulator (GEMS). Simulation results show that the overall performance slowdown is 4 percent on average with the highest keystream hit rate of 78 percent.
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i2sems interconnects independent security enhanced Shared Memory Multiprocessor systems
International Conference on Parallel Architectures and Compilation Techniques, 2007Co-Authors: Manhee Lee, Minseon Ahn, Eun Jung KimAbstract:Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure Memory and cache-to-cache communications in Shared Memory Multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coherence protocols, we refer to it as interconnects-independent security enhanced Shared Memory Multiprocessor systems (I2SEMS). The main challenge in designing I2SEMS is how to precompute keystreams in a timely manner, which is critical to minimize performance overhead. We achieve this goal by adopting a single system-wide global counter controller (GCC) and three additional components for each processor: a key stream queue, a key stream cache, and a key stream pool. The GCC assigns a unique range of counters as a way to help processors precompute the counters' keystreams. We have implemented I2SEMS using Simics with Wisconsin multifacet general execution-driven Multiprocessor simulator (GEMS). We tested our design with SPLASH-2 benchmarks on up to 16-processor Shared Memory Multiprocessor systems. Simulation results show that the overall performance slowdown is 4% on average and the keystream hit rate is as high as 78%. The stable keystream hit rate shows that PSEMS works well with both Memory-read and Memory-write dominant applications. Similar to the conventional cache, a large keystream pool size is beneficial to high hit rates.
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PACT - I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems
2007Co-Authors: Manhee Lee, Minseon Ahn, Eun Jung KimAbstract:Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure Memory and cache-to-cache communications in Shared Memory Multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coherence protocols, we refer to it as interconnects-independent security enhanced Shared Memory Multiprocessor systems (I2SEMS). The main challenge in designing I2SEMS is how to precompute keystreams in a timely manner, which is critical to minimize performance overhead. We achieve this goal by adopting a single system-wide global counter controller (GCC) and three additional components for each processor: a key stream queue, a key stream cache, and a key stream pool. The GCC assigns a unique range of counters as a way to help processors precompute the counters' keystreams. We have implemented I2SEMS using Simics with Wisconsin multifacet general execution-driven Multiprocessor simulator (GEMS). We tested our design with SPLASH-2 benchmarks on up to 16-processor Shared Memory Multiprocessor systems. Simulation results show that the overall performance slowdown is 4% on average and the keystream hit rate is as high as 78%. The stable keystream hit rate shows that PSEMS works well with both Memory-read and Memory-write dominant applications. Similar to the conventional cache, a large keystream pool size is beneficial to high hit rates.
Manhee Lee - One of the best experts on this subject based on the ideXlab platform.
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Fast Secure Communications in Shared Memory Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems, 2011Co-Authors: Manhee Lee, Minseon Ahn, Eun Jung KimAbstract:Protection and security are becoming essential requirements in commercial servers. To provide secure Memory and cache-to-cache communications, we presented Interconnect-Independent Security Enhanced Shared Memory Multiprocessor System (I2SEMS), mainly focusing on how to manage a global counter to encrypt, decrypt, and authenticate data messages with little performance overhead. However, I2SEMS was vulnerable to replay attacks on data messages and integrity attacks on control and counter messages. This paper proposes three authentication schemes to remove those security vulnerabilities. First, we prevent replay attacks on data messages by inserting Request Counter (RC) into request messages. Second, we also use RC to detect integrity attacks on control messages. Third, we propose a new counter, referred to as GCC Counter (GC), to protect the global counter messages. We simulated our design with SPLASH-2 benchmarks on up to 16-processor Shared Memory Multiprocessor systems by using Simics with Wisconsin multifacet General Execution-driven Multiprocessor Simulator (GEMS). Simulation results show that the overall performance slowdown is 4 percent on average with the highest keystream hit rate of 78 percent.
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i2sems interconnects independent security enhanced Shared Memory Multiprocessor systems
International Conference on Parallel Architectures and Compilation Techniques, 2007Co-Authors: Manhee Lee, Minseon Ahn, Eun Jung KimAbstract:Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure Memory and cache-to-cache communications in Shared Memory Multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coherence protocols, we refer to it as interconnects-independent security enhanced Shared Memory Multiprocessor systems (I2SEMS). The main challenge in designing I2SEMS is how to precompute keystreams in a timely manner, which is critical to minimize performance overhead. We achieve this goal by adopting a single system-wide global counter controller (GCC) and three additional components for each processor: a key stream queue, a key stream cache, and a key stream pool. The GCC assigns a unique range of counters as a way to help processors precompute the counters' keystreams. We have implemented I2SEMS using Simics with Wisconsin multifacet general execution-driven Multiprocessor simulator (GEMS). We tested our design with SPLASH-2 benchmarks on up to 16-processor Shared Memory Multiprocessor systems. Simulation results show that the overall performance slowdown is 4% on average and the keystream hit rate is as high as 78%. The stable keystream hit rate shows that PSEMS works well with both Memory-read and Memory-write dominant applications. Similar to the conventional cache, a large keystream pool size is beneficial to high hit rates.
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PACT - I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems
2007Co-Authors: Manhee Lee, Minseon Ahn, Eun Jung KimAbstract:Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure Memory and cache-to-cache communications in Shared Memory Multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coherence protocols, we refer to it as interconnects-independent security enhanced Shared Memory Multiprocessor systems (I2SEMS). The main challenge in designing I2SEMS is how to precompute keystreams in a timely manner, which is critical to minimize performance overhead. We achieve this goal by adopting a single system-wide global counter controller (GCC) and three additional components for each processor: a key stream queue, a key stream cache, and a key stream pool. The GCC assigns a unique range of counters as a way to help processors precompute the counters' keystreams. We have implemented I2SEMS using Simics with Wisconsin multifacet general execution-driven Multiprocessor simulator (GEMS). We tested our design with SPLASH-2 benchmarks on up to 16-processor Shared Memory Multiprocessor systems. Simulation results show that the overall performance slowdown is 4% on average and the keystream hit rate is as high as 78%. The stable keystream hit rate shows that PSEMS works well with both Memory-read and Memory-write dominant applications. Similar to the conventional cache, a large keystream pool size is beneficial to high hit rates.
Mark S. Squillante - One of the best experts on this subject based on the ideXlab platform.
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Using processor-cache affinity information in Shared-Memory Multiprocessor scheduling
IEEE Transactions on Parallel and Distributed Systems, 1993Co-Authors: Mark S. Squillante, Edward D. LazowskaAbstract:In a Shared-Memory Multiprocessor system, it may be more efficient to schedule a task on one processor than on another if relevant data already reside in a particular processor's cache. The effects of this type of processor affinity are examined. It is observed that tasks continuously alternate between executing at a processor and releasing this processor due to I/O, synchronization, quantum expiration, or preemption. Queuing network models of different abstract scheduling policies are formulated, spanning the range from ignoring affinity to fixing tasks on processors. These models are solved via mean value analysis, where possible, and by simulation otherwise. An analytic cache model is developed and used in these scheduling models to include the effects of an initial burst of cache misses experienced by tasks when they return to a processor for execution. A mean-value technique is also developed and used in the scheduling models to include the effects of increased bus traffic due to these bursts of cache misses. Only a small amount of affinity information needs to be maintained for each task. The importance of having a policy that adapts its behavior to changes in system load is demonstrated. >
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analysis of task migration in Shared Memory Multiprocessor scheduling
Measurement and Modeling of Computer Systems, 1991Co-Authors: Mark S. Squillante, Randolph NelsonAbstract:In Shared-Memory Multiprocessor systems it may be more efficient to schedule a task on one processor than on mother. Due to the inevitability of idle processors in these environments, there exists an important tradeoff between keeping the workload balanced and scheduling tasks where they run most efficiently. The purpose of an adaptive task migration policy is to determine the appropriate balance between the extremes of this load sharing tradeoff.We make the observation that there are considerable differences between this load sharing problem in distributed and Shared-Memory Multiprocessor systems, and we formulate a queueing theoretic model of task migration to study the problem. A detailed mathematical analysis of the model is developed, which includes the effects of increased contention for system resources induced by the task migration policy. Our objective is to provide a better understanding of task migration in Shared-Memory Multiprocessor environments. In particular, we illustrate the potential for significant improvements in system performance, and we show that even when migration costs are large it may still be beneficial to migrate waiting tasks to idle processors. We further demonstrate the potential for unstable behavior under migratory scheduling policies, and we provide optimal policy thresholds that yield the best performance and avoid this form of processor thrashing.
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SIGMETRICS - Analysis of task migration in Shared-Memory Multiprocessor scheduling
Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems - SIGMETRICS '91, 1991Co-Authors: Mark S. Squillante, Randolph NelsonAbstract:In Shared-Memory Multiprocessor systems it may be more efficient to schedule a task on one processor than on mother. Due to the inevitability of idle processors in these environments, there exists an important tradeoff between keeping the workload balanced and scheduling tasks where they run most efficiently. The purpose of an adaptive task migration policy is to determine the appropriate balance between the extremes of this load sharing tradeoff.We make the observation that there are considerable differences between this load sharing problem in distributed and Shared-Memory Multiprocessor systems, and we formulate a queueing theoretic model of task migration to study the problem. A detailed mathematical analysis of the model is developed, which includes the effects of increased contention for system resources induced by the task migration policy. Our objective is to provide a better understanding of task migration in Shared-Memory Multiprocessor environments. In particular, we illustrate the potential for significant improvements in system performance, and we show that even when migration costs are large it may still be beneficial to migrate waiting tasks to idle processors. We further demonstrate the potential for unstable behavior under migratory scheduling policies, and we provide optimal policy thresholds that yield the best performance and avoid this form of processor thrashing.
Gernot Heiser - One of the best experts on this subject based on the ideXlab platform.
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vnuma a virtual Shared Memory Multiprocessor
USENIX Annual Technical Conference, 2009Co-Authors: Matthew Chapman, Gernot HeiserAbstract:vNUMA, for virtual NUMA, is a virtual machine that presents a cluster as a virtual Shared-Memory Multiprocessor. It is designed to make the computational power of clusters available to legacy applications and operating systems. A characteristic aspect of vNUMA is that it incorporates distributed Shared Memory (DSM) inside the hypervisor, in contrast to the more traditional approach of providing it in middleware. We present the design of vNUMA, as well as an implementation on Itaniumbased workstations. We discuss in detail the enhancements to standard protocols that were required or enabled when implementing DSM inside a hypervisor, and discuss some of the tradeoffs we encountered. We examine the scalability of vNUMA on a small cluster, and analyse some of the design choices.
James H. Anderson - One of the best experts on this subject based on the ideXlab platform.
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Reader-Writer Synchronization for Shared-Memory Multiprocessor Real-Time Systems
2009 21st Euromicro Conference on Real-Time Systems, 2009Co-Authors: Björn B. Brandenburg, James H. AndersonAbstract:Reader preference, writer preference, and task-fair reader writer locks are shown to cause undue blocking in Multiprocessor real-time systems. A new phase-fair reader-writer lock is proposed as an alternative that significantly reduces worst case blocking for readers and an efficient local-spin implementation is provided. Both task- and phase-fair locks are evaluated and contrasted to mutex locks in terms of hard and soft real-time schedulability under consideration of runtime overheads on a multicore computer.