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Tsunghsien Lin - One of the best experts on this subject based on the ideXlab platform.
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a continuous time delta sigma modulator using eld compensation embedded sab and dwa inherent time domain quantizer
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Tsunghsien LinAbstract:This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a Single-Amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two Amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.
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a 13 mhz 68 db sndr ctdsm using sab loop filter and interpolating flash quantizer with random skip idwa function in 90 nm cmos
Asian Solid-State Circuits Conference, 2015Co-Authors: Chanhsiang Weng, Weihsiang Huang, Erkan Alpman, Tsunghsien LinAbstract:A 4th-order 4-bit continuous-time delta-sigma modulator (CTDSM) employing Single-Amplifier biquad (SAB) based loop filter and an interpolating quantizer is presented. By adopting the SAB-based topology, the proposed loop filter achieves 4th-order noise shaping function with only two op-amps. Furthermore, the proposed twin-T SAB minimizes the latency of the excess loop delay (ELD) compensation path (s0) and 1st-order path (s−1), which achieves better system stability. A low-power interpolating flash quantizer with an embedded random-skip incremental data weighted averaging (RS-IDWA) function is also proposed to address the nonlinearity of the quantizer and feedback DACs. With this technique, signal-dependent harmonic tones induced by the conventional DWA are avoided. Fabricated in a 90-nm CMOS, the proposed CTDSM achieves a peak SNDR of 68 dB over 13-MHz signal bandwidth, while consuming 5.1 mW at 320-MHz sampling frequency. The FoM is 95 fJ/conv.-step.
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an 8 5mhz 67 2db sndr ctdsm with eld compensation embedded twin t sab and circular tdc based quantizer in 90nm cmos
Symposium on VLSI Circuits, 2014Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Yiting Tseng, Tsunghsien LinAbstract:A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a Single-Amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
Chanhsiang Weng - One of the best experts on this subject based on the ideXlab platform.
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a continuous time delta sigma modulator using eld compensation embedded sab and dwa inherent time domain quantizer
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Tsunghsien LinAbstract:This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a Single-Amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two Amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.
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a 13 mhz 68 db sndr ctdsm using sab loop filter and interpolating flash quantizer with random skip idwa function in 90 nm cmos
Asian Solid-State Circuits Conference, 2015Co-Authors: Chanhsiang Weng, Weihsiang Huang, Erkan Alpman, Tsunghsien LinAbstract:A 4th-order 4-bit continuous-time delta-sigma modulator (CTDSM) employing Single-Amplifier biquad (SAB) based loop filter and an interpolating quantizer is presented. By adopting the SAB-based topology, the proposed loop filter achieves 4th-order noise shaping function with only two op-amps. Furthermore, the proposed twin-T SAB minimizes the latency of the excess loop delay (ELD) compensation path (s0) and 1st-order path (s−1), which achieves better system stability. A low-power interpolating flash quantizer with an embedded random-skip incremental data weighted averaging (RS-IDWA) function is also proposed to address the nonlinearity of the quantizer and feedback DACs. With this technique, signal-dependent harmonic tones induced by the conventional DWA are avoided. Fabricated in a 90-nm CMOS, the proposed CTDSM achieves a peak SNDR of 68 dB over 13-MHz signal bandwidth, while consuming 5.1 mW at 320-MHz sampling frequency. The FoM is 95 fJ/conv.-step.
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an 8 5mhz 67 2db sndr ctdsm with eld compensation embedded twin t sab and circular tdc based quantizer in 90nm cmos
Symposium on VLSI Circuits, 2014Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Yiting Tseng, Tsunghsien LinAbstract:A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a Single-Amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
Erkan Alpman - One of the best experts on this subject based on the ideXlab platform.
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a continuous time delta sigma modulator using eld compensation embedded sab and dwa inherent time domain quantizer
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Tsunghsien LinAbstract:This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a Single-Amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two Amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.
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a 13 mhz 68 db sndr ctdsm using sab loop filter and interpolating flash quantizer with random skip idwa function in 90 nm cmos
Asian Solid-State Circuits Conference, 2015Co-Authors: Chanhsiang Weng, Weihsiang Huang, Erkan Alpman, Tsunghsien LinAbstract:A 4th-order 4-bit continuous-time delta-sigma modulator (CTDSM) employing Single-Amplifier biquad (SAB) based loop filter and an interpolating quantizer is presented. By adopting the SAB-based topology, the proposed loop filter achieves 4th-order noise shaping function with only two op-amps. Furthermore, the proposed twin-T SAB minimizes the latency of the excess loop delay (ELD) compensation path (s0) and 1st-order path (s−1), which achieves better system stability. A low-power interpolating flash quantizer with an embedded random-skip incremental data weighted averaging (RS-IDWA) function is also proposed to address the nonlinearity of the quantizer and feedback DACs. With this technique, signal-dependent harmonic tones induced by the conventional DWA are avoided. Fabricated in a 90-nm CMOS, the proposed CTDSM achieves a peak SNDR of 68 dB over 13-MHz signal bandwidth, while consuming 5.1 mW at 320-MHz sampling frequency. The FoM is 95 fJ/conv.-step.
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an 8 5mhz 67 2db sndr ctdsm with eld compensation embedded twin t sab and circular tdc based quantizer in 90nm cmos
Symposium on VLSI Circuits, 2014Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Yiting Tseng, Tsunghsien LinAbstract:A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a Single-Amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
Tzuan Wei - One of the best experts on this subject based on the ideXlab platform.
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a continuous time delta sigma modulator using eld compensation embedded sab and dwa inherent time domain quantizer
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Tsunghsien LinAbstract:This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a Single-Amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two Amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.
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an 8 5mhz 67 2db sndr ctdsm with eld compensation embedded twin t sab and circular tdc based quantizer in 90nm cmos
Symposium on VLSI Circuits, 2014Co-Authors: Chanhsiang Weng, Erkan Alpman, Tzuan Wei, Yiting Tseng, Tsunghsien LinAbstract:A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a Single-Amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
T S Fiez - One of the best experts on this subject based on the ideXlab platform.
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an 80 db dr 7 2 mhz bandwidth Single opamp biquad based ct delta sigma modulator dissipating 13 7 mw
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Ramin Zanbaghi, Pavan Kumar Hanumolu, T S FiezAbstract:A novel low power compact loop filter using a Single Amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram. By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology. Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture. The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator. The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs). A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques. Within a 7.2 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 83.1 dB, respectively, and the total power consumption of 13.7 mW.
