The Experts below are selected from a list of 1263 Experts worldwide ranked by ideXlab platform
Shengchi Wu - One of the best experts on this subject based on the ideXlab platform.
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the construction of binary huffman equivalent codes with a greater number of synchronising codewords
Ubiquitous Computing, 2012Co-Authors: Yuhming Huang, Shengchi WuAbstract:An inherent problem with a Variable-Length Code (VLC) is that even a Single Bit Error can cause a loss of synchronisation, and thus lead to Error propagation. Codeword synchronisation has been extensively studied as a means to overcome this drawback and efficiently stop Error propagation. In this paper, we first present the sufficient and necessary conditions for the existence of binary Huffman equivalent codes with the shortest, or at most two shortest, synchronising codeword(s) of length m + 1, where m (>1) is the shortest codeword length. Next, based on the results, we propose a unified approach for constructing each of these binary Huffman equivalent codes with the shortest, or at most two shortest, synchronising codeword(s) of length m + 1, if such a code exists for a given length vector.
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shortest synchronizing codewords of a binary huffman equivalent code
International Conference on Information Technology: Coding and Computing, 2003Co-Authors: Yuhming Huang, Shengchi WuAbstract:The inherent problem of a variable-length code is that even a Single Bit Error can cause loss of synchronization and may lead to Error propagation. Synchronizing codewords have been extensively studies as a mean to overcome the drawback and efficiently stop Error propagation. First we prove the restatement of a result originally given by B. Ruder (1971) in a more straightforward way. Next, we present the necessary conditions for the existence of a binary Huffman equivalent code with shortest synchronizing codeword(s). Finally, with the help of derived conditional equations, a unified approach for constructing a binary Huffman equivalent code with most shortest synchronizing codeword(s) and most other synchronizing codewords is proposed also.
Yuhming Huang - One of the best experts on this subject based on the ideXlab platform.
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the construction of binary huffman equivalent codes with a greater number of synchronising codewords
Ubiquitous Computing, 2012Co-Authors: Yuhming Huang, Shengchi WuAbstract:An inherent problem with a Variable-Length Code (VLC) is that even a Single Bit Error can cause a loss of synchronisation, and thus lead to Error propagation. Codeword synchronisation has been extensively studied as a means to overcome this drawback and efficiently stop Error propagation. In this paper, we first present the sufficient and necessary conditions for the existence of binary Huffman equivalent codes with the shortest, or at most two shortest, synchronising codeword(s) of length m + 1, where m (>1) is the shortest codeword length. Next, based on the results, we propose a unified approach for constructing each of these binary Huffman equivalent codes with the shortest, or at most two shortest, synchronising codeword(s) of length m + 1, if such a code exists for a given length vector.
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shortest synchronizing codewords of a binary huffman equivalent code
International Conference on Information Technology: Coding and Computing, 2003Co-Authors: Yuhming Huang, Shengchi WuAbstract:The inherent problem of a variable-length code is that even a Single Bit Error can cause loss of synchronization and may lead to Error propagation. Synchronizing codewords have been extensively studies as a mean to overcome the drawback and efficiently stop Error propagation. First we prove the restatement of a result originally given by B. Ruder (1971) in a more straightforward way. Next, we present the necessary conditions for the existence of a binary Huffman equivalent code with shortest synchronizing codeword(s). Finally, with the help of derived conditional equations, a unified approach for constructing a binary Huffman equivalent code with most shortest synchronizing codeword(s) and most other synchronizing codewords is proposed also.
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ITCC - Shortest synchronizing codewords of a binary Huffman equivalent code
Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing, 1Co-Authors: Yuhming HuangAbstract:The inherent problem of a variable-length code is that even a Single Bit Error can cause loss of synchronization and may lead to Error propagation. Synchronizing codewords have been extensively studies as a mean to overcome the drawback and efficiently stop Error propagation. First we prove the restatement of a result originally given by B. Ruder (1971) in a more straightforward way. Next, we present the necessary conditions for the existence of a binary Huffman equivalent code with shortest synchronizing codeword(s). Finally, with the help of derived conditional equations, a unified approach for constructing a binary Huffman equivalent code with most shortest synchronizing codeword(s) and most other synchronizing codewords is proposed also.
J Del Ser - One of the best experts on this subject based on the ideXlab platform.
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fast and accurate Single Bit Error injection into sram based fpgas
Field-Programmable Logic and Applications, 2012Co-Authors: Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, M Garay, J Del SerAbstract:The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of Errors. One Error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal Error injection are used to emulate this kind of Error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.
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FPL - Fast and accurate Single Bit Error injection into SRAM Based FPGAs
22nd International Conference on Field Programmable Logic and Applications (FPL), 2012Co-Authors: Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, M Garay, J Del SerAbstract:The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of Errors. One Error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal Error injection are used to emulate this kind of Error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.
M. Biskup - One of the best experts on this subject based on the ideXlab platform.
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ITW - A word that does not appear in encoded message as a resynchronization marker
2008 IEEE Information Theory Workshop, 2008Co-Authors: M. BiskupAbstract:In case of variable-length codes a Single Bit Error may cause loss of synchronization at the decoder and thus may lead to Error propagation. Even if the decoder resynchronizes after a number of Bits, it may have decoded incorrect number of symbols and may place the further decoded symbols at wrong positions. This paper describes a method for choosing such string of Bits ws that the decoder can always recognize any insertions of ws into the encoded message and reestablish synchronization. ws will be constructed of the shortest word that is not a substring of the encoded message. The method does not require any modification of the code.
Uli Kretzschmar - One of the best experts on this subject based on the ideXlab platform.
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fast and accurate Single Bit Error injection into sram based fpgas
Field-Programmable Logic and Applications, 2012Co-Authors: Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, M Garay, J Del SerAbstract:The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of Errors. One Error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal Error injection are used to emulate this kind of Error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.
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FPL - Fast and accurate Single Bit Error injection into SRAM Based FPGAs
22nd International Conference on Field Programmable Logic and Applications (FPL), 2012Co-Authors: Uli Kretzschmar, Armando Astarloa, Jaime Jimenez, M Garay, J Del SerAbstract:The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of Errors. One Error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal Error injection are used to emulate this kind of Error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.
