The Experts below are selected from a list of 36 Experts worldwide ranked by ideXlab platform

Katherine Compton - One of the best experts on this subject based on the ideXlab platform.

  • FPT - A scalable memory interface for multicore reconfigurable computing systems
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Philip Garcia, Katherine Compton
    Abstract:

    Embedded multicore devices require high performance with minimal power consumption; many systems use dedicated hardware units to meet these constraints. However, embedded systems have also become increasingly multi-purpose and must be able to execute a wide range of applications — some of which might not yet be known at design time. It is therefore difficult to choose an appropriate mix of dedicated hardware that meets a device's size, cost, and capability constraints. A reconfigurable hardware Coprocessor is a potential solution, as it is highly effective at accelerating a variety of different tasks (which need not necessarily be known in advance), and does so using less energy than general purpose processors. In this work, we first describe a method for sharing a Single reconfigurable fabric amongst multiple processors on the same chip. We then examine the scalability of the memory subsystem that joins these resources, and determine methods to improve its performance to maximize acceleration. In this work, we show that our RH Coprocessor model allows multiple applications to share a Single RH fabric. Furthermore, we show that application performance does not significantly degrade as we increase the number of cores sharing a Single Coprocessor.

  • A scalable memory interface for multicore reconfigurable computing systems
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Philip Garcia, Katherine Compton
    Abstract:

    Embedded multicore devices require high performance with minimal power consumption; many systems use dedicated hardware units to meet these constraints. However, embedded systems have also become increasingly multi-purpose and must be able to execute a wide range of applications - some of which might not yet be known at design time. It is therefore difficult to choose an appropriate mix of dedicated hardware that meets a device's size, cost, and capability constraints. A reconfigurable hardware Coprocessor is a potential solution, as it is highly effective at accelerating a variety of different tasks (which need not necessarily be known in advance), and does so using less energy than general purpose processors. In this work, we first describe a method for sharing a Single reconfigurable fabric amongst multiple processors on the same chip. We then examine the scalability of the memory subsystem that joins these resources, and determine methods to improve its performance to maximize acceleration. In this work, we show that our RH Coprocessor model allows multiple applications to share a Single RH fabric. Furthermore, we show that application performance does not significantly degrade as we increase the number of cores sharing a Single Coprocessor.

Nicol So - One of the best experts on this subject based on the ideXlab platform.

  • Secure open systems for protecting privacy and digital services
    Lecture Notes in Computer Science, 2020
    Co-Authors: David W. Kravitz, Kim-ee Yeoh, Nicol So
    Abstract:

    This paper describes and analyzes a system architecture that enables consumers to access services and content from multiple providers without jeopardizing the privacy interests of consumers or the intellectual property rights of providers. In order to satisfy these highly desirable objectives, we argue for the necessity of a Trust Server that mediates the conferral and revocation of trust relationships between consumers and providers. The system also calls for the deployment of programmable security Coprocessors at vulnerable sites requiring protection, namely at the Trust Server and at each consumer. We define the specific requirements of consumer-side Coprocessors, and their server-side counterparts denoted as Hardware Security Modules (HSMs). A Single Coprocessor serves multiple providers by allocating to each of them a virtualized trusted computing environment for software execution and data manipulation. Bearing in mind that the tamper-resistance offered by Coprocessors is subject to more stringent economic pressures than that offered by HSMs, we include in our architecture containment capabilities that prevent compromised Coprocessors from causing damage disproportionate to their numbers. We explain the specific challenges faced with providing containment capabilities while protecting consumer privacy, given that a Single Coprocessor must serve the needs of multiple providers. The simultaneous attainment of these goals is one of the highlights of our architecture.

  • Digital Rights Management Workshop - Secure Open Systems for Protecting Privacy and Digital Services
    Security and Privacy in Digital Rights Management, 2002
    Co-Authors: David W. Kravitz, Kim-ee Yeoh, Nicol So
    Abstract:

    This paper describes and analyzes a system architecture that enables consumers to access services and content from multiple providers without jeopardizing the privacy interests of consumers or the intellectual property rights of providers. In order to satisfy these highly desirable objectives, we argue for the necessity of a Trust Server that mediates the conferral and revocation of trust relationships between consumers and providers. The system also calls for the deployment of programmable security Coprocessors at vulnerable sites requiring protection, namely at the Trust Server and at each consumer. We define the specific requirements of consumer-side Coprocessors, and their server-side counterparts denoted as Hardware Security Modules (HSMs). A Single Coprocessor serves multiple providers by allocating to each of them a virtualized trusted computing environment for software execution and data manipulation. Bearing in mind that the tamper-resistance offered by Coprocessors is subject to more stringent economic pressures than that offered by HSMs, we include in our architecture containment capabilities that prevent compromised Coprocessors from causing damage disproportionate to their numbers. We explain the specific challenges faced with providing containment capabilities while protecting consumer privacy, given that a Single Coprocessor must serve the needs of multiple providers. The simultaneous attainment of these goals is one of the highlights of our architecture.

Philip Garcia - One of the best experts on this subject based on the ideXlab platform.

  • FPT - A scalable memory interface for multicore reconfigurable computing systems
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Philip Garcia, Katherine Compton
    Abstract:

    Embedded multicore devices require high performance with minimal power consumption; many systems use dedicated hardware units to meet these constraints. However, embedded systems have also become increasingly multi-purpose and must be able to execute a wide range of applications — some of which might not yet be known at design time. It is therefore difficult to choose an appropriate mix of dedicated hardware that meets a device's size, cost, and capability constraints. A reconfigurable hardware Coprocessor is a potential solution, as it is highly effective at accelerating a variety of different tasks (which need not necessarily be known in advance), and does so using less energy than general purpose processors. In this work, we first describe a method for sharing a Single reconfigurable fabric amongst multiple processors on the same chip. We then examine the scalability of the memory subsystem that joins these resources, and determine methods to improve its performance to maximize acceleration. In this work, we show that our RH Coprocessor model allows multiple applications to share a Single RH fabric. Furthermore, we show that application performance does not significantly degrade as we increase the number of cores sharing a Single Coprocessor.

  • A scalable memory interface for multicore reconfigurable computing systems
    2011 International Conference on Field-Programmable Technology, 2011
    Co-Authors: Philip Garcia, Katherine Compton
    Abstract:

    Embedded multicore devices require high performance with minimal power consumption; many systems use dedicated hardware units to meet these constraints. However, embedded systems have also become increasingly multi-purpose and must be able to execute a wide range of applications - some of which might not yet be known at design time. It is therefore difficult to choose an appropriate mix of dedicated hardware that meets a device's size, cost, and capability constraints. A reconfigurable hardware Coprocessor is a potential solution, as it is highly effective at accelerating a variety of different tasks (which need not necessarily be known in advance), and does so using less energy than general purpose processors. In this work, we first describe a method for sharing a Single reconfigurable fabric amongst multiple processors on the same chip. We then examine the scalability of the memory subsystem that joins these resources, and determine methods to improve its performance to maximize acceleration. In this work, we show that our RH Coprocessor model allows multiple applications to share a Single RH fabric. Furthermore, we show that application performance does not significantly degrade as we increase the number of cores sharing a Single Coprocessor.

David W. Kravitz - One of the best experts on this subject based on the ideXlab platform.

  • Secure open systems for protecting privacy and digital services
    Lecture Notes in Computer Science, 2020
    Co-Authors: David W. Kravitz, Kim-ee Yeoh, Nicol So
    Abstract:

    This paper describes and analyzes a system architecture that enables consumers to access services and content from multiple providers without jeopardizing the privacy interests of consumers or the intellectual property rights of providers. In order to satisfy these highly desirable objectives, we argue for the necessity of a Trust Server that mediates the conferral and revocation of trust relationships between consumers and providers. The system also calls for the deployment of programmable security Coprocessors at vulnerable sites requiring protection, namely at the Trust Server and at each consumer. We define the specific requirements of consumer-side Coprocessors, and their server-side counterparts denoted as Hardware Security Modules (HSMs). A Single Coprocessor serves multiple providers by allocating to each of them a virtualized trusted computing environment for software execution and data manipulation. Bearing in mind that the tamper-resistance offered by Coprocessors is subject to more stringent economic pressures than that offered by HSMs, we include in our architecture containment capabilities that prevent compromised Coprocessors from causing damage disproportionate to their numbers. We explain the specific challenges faced with providing containment capabilities while protecting consumer privacy, given that a Single Coprocessor must serve the needs of multiple providers. The simultaneous attainment of these goals is one of the highlights of our architecture.

  • Digital Rights Management Workshop - Secure Open Systems for Protecting Privacy and Digital Services
    Security and Privacy in Digital Rights Management, 2002
    Co-Authors: David W. Kravitz, Kim-ee Yeoh, Nicol So
    Abstract:

    This paper describes and analyzes a system architecture that enables consumers to access services and content from multiple providers without jeopardizing the privacy interests of consumers or the intellectual property rights of providers. In order to satisfy these highly desirable objectives, we argue for the necessity of a Trust Server that mediates the conferral and revocation of trust relationships between consumers and providers. The system also calls for the deployment of programmable security Coprocessors at vulnerable sites requiring protection, namely at the Trust Server and at each consumer. We define the specific requirements of consumer-side Coprocessors, and their server-side counterparts denoted as Hardware Security Modules (HSMs). A Single Coprocessor serves multiple providers by allocating to each of them a virtualized trusted computing environment for software execution and data manipulation. Bearing in mind that the tamper-resistance offered by Coprocessors is subject to more stringent economic pressures than that offered by HSMs, we include in our architecture containment capabilities that prevent compromised Coprocessors from causing damage disproportionate to their numbers. We explain the specific challenges faced with providing containment capabilities while protecting consumer privacy, given that a Single Coprocessor must serve the needs of multiple providers. The simultaneous attainment of these goals is one of the highlights of our architecture.

Martin Berzins - One of the best experts on this subject based on the ideXlab platform.

  • chapter 13 exploring use of the reserved core
    High Performance Parallelism Pearls#R##N#Volume 2: Multicore and Many-core Programming Approaches, 2015
    Co-Authors: John K Holmen, Alan Humphrey, Martin Berzins
    Abstract:

    In this chapter, we illustrate benefits of thinking in terms of thread management techniques when using a centralized scheduler model along with interoperability of MPI and PThread. This is facilitated through an exploration of thread placement strategies for an algorithm modeling radiative heat transfer with special attention to the 61st core. This algorithm plays a key role within the Uintah Computational Framework (UCF) and current efforts taking place at the University of Utah to model next-generation, large-scale clean coal boilers. In such simulations, this algorithm models the dominant form of heat transfer and consumes a large portion of compute time. Exemplified by a real-world example, this chapter presents our early efforts in porting a key portion of a scalability-centric codebase to the Intel Xeon Phi Coprocessor. Specifically, this chapter presents results from our experiments profiling the native execution of a reverse Monte-Carlo ray tracing-based radiation model on a Single Coprocessor. These results demonstrate that our fastest run configurations utilized the 61st core and that performance was not profoundly impacted when explicitly oversubscribing the Coprocessor operating system thread. Additionally, this chapter presents a portion of radiation model source code, a MIC-centric UCF cross-compilation example, and less conventional thread management technique formore » developers utilizing the PThreads threading model.« less

  • Chapter 13 – Exploring Use of the Reserved Core
    2015
    Co-Authors: John K Holmen, Alan Humphrey, Martin Berzins
    Abstract:

    In this chapter, we illustrate benefits of thinking in terms of thread management techniques when using a centralized scheduler model along with interoperability of MPI and PThread. This is facilitated through an exploration of thread placement strategies for an algorithm modeling radiative heat transfer with special attention to the 61st core. This algorithm plays a key role within the Uintah Computational Framework (UCF) and current efforts taking place at the University of Utah to model next-generation, large-scale clean coal boilers. In such simulations, this algorithm models the dominant form of heat transfer and consumes a large portion of compute time. Exemplified by a real-world example, this chapter presents our early efforts in porting a key portion of a scalability-centric codebase to the Intel Xeon Phi Coprocessor. Specifically, this chapter presents results from our experiments profiling the native execution of a reverse Monte-Carlo ray tracing-based radiation model on a Single Coprocessor. These results demonstrate that our fastest run configurations utilized the 61st core and that performance was not profoundly impacted when explicitly oversubscribing the Coprocessor operating system thread. Additionally, this chapter presents a portion of radiation model source code, a MIC-centric UCF cross-compilation example, and less conventional thread management technique formore » developers utilizing the PThreads threading model.« less