The Experts below are selected from a list of 61575 Experts worldwide ranked by ideXlab platform
Soni Chaturvedi - One of the best experts on this subject based on the ideXlab platform.
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implementation of 32 bit binary floating point adder using ieee 754 single precision Format
2015Co-Authors: Iosr Journals, Rupali Dhobale, Soni ChaturvediAbstract:Field Programmable Gate Arrays (FPGA) are increasingly being used to design highend computationally intense microprocessors capable of handling both fixed and floatingpoint mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating point adder with minimum time. Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL. This paper discusses in detail the best possible FPGA implementation will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
Luca Benini - One of the best experts on this subject based on the ideXlab platform.
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4 6 a 65nm cmos 6 4 to 29 2pj flop 0 8v shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster
International Solid-State Circuits Conference, 2016Co-Authors: Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca BeniniAbstract:Energy-efficient computing and ultra-low-power operation are requirements for many application areas, such as IoT and wearables. While for some applications, integer and fixed-point processor instructions suffice, others (e.g. simultaneous localization and mapping - SLAM, stereo vision, nonlinear regression and classification) require a larger dynamic range, typically obtained using single/double-precision floating point (FP) instructions. Logarithmic number systems (LNS) have been proposed [1,2] as an energy-efficient alternative to conventional FP, as several complex operations such as MUL, DIV, and EXP translate into simpler arithmetic operations in the logarithmic space and can be efficiently calculated using integer arithmetic units. However, ADD and SUB become nonlinear and have to be approximated by look-up tables (LUTs) and interpolation, which is typically implemented in a dedicated LNS unit (LNU) [1,2]. The area of LNUs grows exponentially with the desired precision, and an LNU with accuracy comparable to IEEE Single-Precision Format is larger than a traditional floating-point unit (FPU). However, we show that in multi-core systems optimized for ultra-low-power operation such as the PULP system [3], one LNU can be efficiently shared in a cluster as indicated in Fig. 4.6.1. This arrangement not only reduces the per-core area overhead, but more importantly, allows several costly operations such as FP MUL/DIV to be processed without contention within the integer cores without additional overhead. We show that for typical nonlinear processing tasks, our LNU design can be up to 4.2× more energy efficient than a private-FP design.
Iosr Journals - One of the best experts on this subject based on the ideXlab platform.
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implementation of 32 bit binary floating point adder using ieee 754 single precision Format
2015Co-Authors: Iosr Journals, Rupali Dhobale, Soni ChaturvediAbstract:Field Programmable Gate Arrays (FPGA) are increasingly being used to design highend computationally intense microprocessors capable of handling both fixed and floatingpoint mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating point adder with minimum time. Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL. This paper discusses in detail the best possible FPGA implementation will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
Padmapriya Patil - One of the best experts on this subject based on the ideXlab platform.
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A High Speed Binary Single Precision Floating Point Multiplier Using Dadda Algorithm and Parallel Prefix Adder Mr. Shailesh Kumar
2016Co-Authors: Padmapriya PatilAbstract:Abstract--- Floating Point Arithmetic is extensively used in the field of Digital signal processing, Medical imaging, motion capture, audio application including broadcast and musical instruments.Many of these applications need to solve linear systems that use fair amount of matrix multiplication. The multiplier conforms to the IEEE 754 standard for single precision. The IEEE standard for Binary Floating point Arithmetic (IEEE 754)is most widely used standard for Floating point computation and is followed by many CPU and FPU implementation. An algorithm called Dadda algorithm is introduced here for reducing the partial product of multiplier unit single precision Format. In this thesis to improve speed of multiplication of mantissa is done by using Dadda algorithm replacing carry save multiplier. The sub-module have been written in Verilog HDL and then synthesized simulated using Xilinx ISE 12.4. To find overall more speed of multiplication of two 32 bit Floating point numbers the exponents of two 32 bit Floating point numbers is calculated as Ea +Eb-127.Here exponent addition takes place by using kogge stone adder instead of Ripple carry adder which is used earlier. Earlier speed was 526 MHZ but the use of Dadda algorithm in mantissa multiplication and kogge stone adder in the exponent calculation increases the speed and reduces the delay time. So the kogge stone adder is faster adder and reduces delay. The Floating point multiplier is developed to handle overflow and underflow cases. Keywords- Dadda algorithm; Single precision Floating point number; multiplication; Verilog HDL
Rupali Dhobale - One of the best experts on this subject based on the ideXlab platform.
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implementation of 32 bit binary floating point adder using ieee 754 single precision Format
2015Co-Authors: Iosr Journals, Rupali Dhobale, Soni ChaturvediAbstract:Field Programmable Gate Arrays (FPGA) are increasingly being used to design highend computationally intense microprocessors capable of handling both fixed and floatingpoint mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating point adder with minimum time. Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL. This paper discusses in detail the best possible FPGA implementation will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.