The Experts below are selected from a list of 162 Experts worldwide ranked by ideXlab platform

D.f. Baldwin - One of the best experts on this subject based on the ideXlab platform.

  • Flux-underfill compatibility and failure mode analysis in high yield flip chip processing
    27th Annual IEEE SEMI International Electronics Manufacturing Technology Symposium, 2002
    Co-Authors: P.n. Houston, D.f. Baldwin, W.m. Tsai
    Abstract:

    The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, Snap Cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to evaluate the reliability of each flux-underfill material system. The failure modes, specifically underfill delamination, solder fatigue, and die cracking, are identified and analyzed. The correlation among process manufacturing defects, failure modes, and long-term reliability are determined. Understanding these failure modes will further enable and facilitate the implementation of low cost, high yield flip chip processing in standard surface mount technology.

  • Processing and reliability of flip chip with lead-free solders on halogen-free microvia substrates
    27th Annual IEEE SEMI International Electronics Manufacturing Technology Symposium, 2002
    Co-Authors: D.f. Baldwin, G. Baynham, K. Boustedt, C. Wennerholm
    Abstract:

    An assembly process for environmentally conscious low cost flip chip assembly to microvia laminate substrates is presented, based on a fully integrated high speed flip chip assembly line. The process includes the flux application, chip placement, reflow process, and underfill processing. Flux and underfill material compatibility is discussed, and data presented analyzing the quality of the solder joint formation and underfill adhesion to halogen-free solder masks. 204-/spl mu/m pitch peripheral bump, daisy chain test chips with edge lengths of 5 mm and 10 mm respectively are used. Comprehensive reliability results, are presented, comparing the two lead-free to tin/lead eutectic interconnect systems. The chips are assembled on microvia substrates with electroless nickel/immersion gold surface finish, comparing conventional to halogen-free FR-4 and solder masks. A fast flow Snap Cure underfill, qualified for use with eutectic tin/lead joints on conventional FR-4, is used for both board types. Reliability results from air-to-air thermal shock testing are presented, comparing lead-free to eutectic interconnect systems mounted on conventional and halogen-free microvia substrates. Process and failure mode analysis are presented, based on X-ray inspection, C-SAM analysis, and assembly cross sections.

  • Flip chip assembly process development, reliability assessment and process characterization for polymer stud grid array-chip scale package
    2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220), 2001
    Co-Authors: C.s. Paydenkar, F.g. Jefferson, D.f. Baldwin
    Abstract:

    The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip scale package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This paper focuses on two key elements of PSGA technology which are: 1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT); and 2) qualifying the reliability performance of flip chip PSGA packages. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow Snap Cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust-high through-put flip chip assembly process and presents preliminary reliability based on air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C) of the assembled PSGA Chip Scale Packages (CSPs).

  • Chip scale polymer stud grid array packaging and reliability based on low cost flip chip processing
    2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070), 2000
    Co-Authors: C.s. Paydenkar, D.f. Baldwin, S. Sitaraman, C.p. Wong, B.j. Lewis
    Abstract:

    The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This package was designed and manufactured in response to a demand for low cost, moderate pin density packages. This paper focuses on two key elements of PSGA technology which are: (1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT), and (2) qualifying the reliability performance of flip chip PSGA modules. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow Snap Cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability based on liquid to liquid thermal cycling (-55/spl deg/C to 125/spl deg/C) of the assembled PSGA Chip Scale Packages (CSPs).

  • Flux-underfill compatibility and failure mode analysis in high yield flip chip processing
    Twenty Sixth IEEE CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146), 2000
    Co-Authors: W.m. Tsai, P.n. Houston, D.f. Baldwin
    Abstract:

    The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, Snap Cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to evaluate the reliability of each flux-underfill material system. The failure modes, specifically underfill delamination, solder fatigue, and die cracking, are identified and analyzed. The correlation between process manufacturing defects, failure modes, and long-term reliability are determined. Understanding these failure modes will further enable and facilitate the implementation of low cost, high yield flip chip processing in standard surface mount technology.

C.s. Paydenkar - One of the best experts on this subject based on the ideXlab platform.

  • Chip scale Polymer Stud Grid Array packaging and reliability based on low cost flip Chip processing
    2020
    Co-Authors: C.s. Paydenkar, D.f. Baldwin, S. Sitaraman, C.p. Wong
    Abstract:

    The Polymer Stud Grid Array (PSGA ) package is a new and unique type of area array chip package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This package was designed and manufactured in response to a demand for low cost, high pin density packages. This paper focuses on two key elements to developing market share for PSGA technology which are: 1) developing high throughput flip chip assembly process technology for CSP-PSGA configurations using existing Surface Mount Technology (SMT) 2) assessing the reliability of assembled flip chip PSGA modules. The interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill material, and flip chip process technology, The underfill materials selected for evaluation are no-flow reflowable, fast flow Snap Cure encapsulants, and high reliability underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability data accumulated during liquid to liquid thermal cycling (-55°C to 125°C) of the assembled Chip Scaled Packages (CSPs).

  • Flip chip assembly process development, reliability assessment and process characterization for polymer stud grid array-chip scale package
    2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220), 2001
    Co-Authors: C.s. Paydenkar, F.g. Jefferson, D.f. Baldwin
    Abstract:

    The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip scale package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This paper focuses on two key elements of PSGA technology which are: 1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT); and 2) qualifying the reliability performance of flip chip PSGA packages. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow Snap Cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust-high through-put flip chip assembly process and presents preliminary reliability based on air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C) of the assembled PSGA Chip Scale Packages (CSPs).

  • Chip scale polymer stud grid array packaging and reliability based on low cost flip chip processing
    2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070), 2000
    Co-Authors: C.s. Paydenkar, D.f. Baldwin, S. Sitaraman, C.p. Wong, B.j. Lewis
    Abstract:

    The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This package was designed and manufactured in response to a demand for low cost, moderate pin density packages. This paper focuses on two key elements of PSGA technology which are: (1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT), and (2) qualifying the reliability performance of flip chip PSGA modules. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow Snap Cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability based on liquid to liquid thermal cycling (-55/spl deg/C to 125/spl deg/C) of the assembled PSGA Chip Scale Packages (CSPs).

D.f. Baldwin - One of the best experts on this subject based on the ideXlab platform.

  • Chip scale Polymer Stud Grid Array packaging and reliability based on low cost flip Chip processing
    2020
    Co-Authors: C.s. Paydenkar, D.f. Baldwin, S. Sitaraman, C.p. Wong
    Abstract:

    The Polymer Stud Grid Array (PSGA ) package is a new and unique type of area array chip package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This package was designed and manufactured in response to a demand for low cost, high pin density packages. This paper focuses on two key elements to developing market share for PSGA technology which are: 1) developing high throughput flip chip assembly process technology for CSP-PSGA configurations using existing Surface Mount Technology (SMT) 2) assessing the reliability of assembled flip chip PSGA modules. The interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill material, and flip chip process technology, The underfill materials selected for evaluation are no-flow reflowable, fast flow Snap Cure encapsulants, and high reliability underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability data accumulated during liquid to liquid thermal cycling (-55°C to 125°C) of the assembled Chip Scaled Packages (CSPs).

  • Compatibility of flux and underfill material systems
    2020
    Co-Authors: W. Mike Tsai, Paul N. Houston, D.f. Baldwin
    Abstract:

    Flip chip assembly is an increasingly utilized process for direct chip attach in surface mount technology (SMT). Currently, there are limited mainstream manufacturing processes integrating flip chip into standard surface mount processes. Because various interconnect materials and methods can be employed to mount the chip onto the substrate, design guidelines and process strategies are crucial for integration with SMT in order to provide high yield and throughput. However, there exist numerous design factors, process variables, and throughput issues that tend to impede the implementation of flip chip processing in surface mount applications. To understand and eliminate these impediments to flip chip commercialization, the process factors and process-induced defects that impact the flip chip process yield must be investigated. Among these concerns, the compatibility of flux and underfill is one of the main challenges that needs to be addressed to provide a robust flip chip process window and acceptable reliability The reliability is governed primarily by solder wettability and electrical continuity. The processes of fluxing, placement, reflow, underfill, and Cure define how a device will perform under long-term reliability assessment. An experimental matrix has been developed to evaluate five no-clean fluxes for both dip and dispense applications baselining them with respect to a water soluble flux and an aqueous cleaning operation. Two commercial fast-flow, Snap-Cure underfills are employed to determine their compatibility with the two down selected fluxes and the control flux. Reliability tests are performed applying liquid-to-liquid thermal shock testing in order to characterize and evaluate the performance of each flux-underfill material system combination.

  • processing and reliability of fast flow Snap Cure underfills part i processing and moisture sensitivity
    IEEE Transactions on Electronics Packaging Manufacturing, 2000
    Co-Authors: D.f. Baldwin, P.n. Houston, M. Deladisma, L.n. Crane, M. Konarski
    Abstract:

    This series of articles studies the processing, moisture sensitivity, reliability, and failure mode analysis of a number of commercial fast-flow, Snap-Cure underfill materials. It includes data on process analysis, processing times, and reliability of the test vehicles in air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C), liquid to liquid thermal shock (-55/spl deg/C to 125/spl deg/C), and J Standard 020 Revision A Level 3 Moisture Sensitivity Preconditioning followed by reliability testing. Samples Cured using a second reflow pass are compared to baseline samples Cured in a standard batch oven based on the underfill manufacturer's recommended Cure schedule. Results from the processing of these new materials have shown a greatly reduced flow time from earlier generation underfill materials as all of these materials had flow times of less than 30 s under 5-mm test die. Through differential scanning calorimetry analysis, it was shown that materials requiring less than 8 min to Cure exhibited at least 95% conversion (percentage of material Cured) through the modified second side renew profile. Some of these commercial underfills have also passed J Standard 020 Revision A Level 3 Moisture Sensitivity testing. Specifically in this paper, the flip chip processing, underfill processing, moisture preconditioning, and preconditioning failure modes are presented.

  • Adhesion characterization of no flow underfill baselined with fast flow Snap Cure
    Proceedings International Symposium on Advanced Packaging Materials Processes Properties and Interfaces (Cat. No.00TH8507), 2000
    Co-Authors: J. Lu, B. Smith, D.f. Baldwin
    Abstract:

    Adhesion of underfill is critical to the reliability of a flip chip assembly. This paper focuses on characterization of underfill adhesion between underfill and Si/sub 3/N/sub 4/ passivated chip based on shear testing. A new die shear test vehicle is developed. The adhesion of a no flow underfill before and after post baking is investigated. It was found that post baking enhances the adhesion of the no flow underfill studied significantly. After post baking, the no flow underfill has similar adhesion to the passivated chip compared to a fast flow Snap Cure underfill used as baselines. In addition, the failure mode in the shear tests shifts from combined adhesive and cohesive failure in non-post-baked samples with no flow underfill, to underfill/substrate interface fracture in post baked samples.

  • Processing and reliability of fast-flow, Snap-Cure underfills. I. Processing and moisture sensitivity
    IEEE Transactions on Electronics Packaging Manufacturing, 2000
    Co-Authors: D.f. Baldwin, P.n. Houston, M. Deladisma, L.n. Crane, M. Konarski
    Abstract:

    This series of articles studies the processing, moisture sensitivity, reliability, and failure mode analysis of a number of commercial fast-flow, Snap-Cure underfill materials. It includes data on process analysis, processing times, and reliability of the test vehicles in air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C), liquid to liquid thermal shock (-55/spl deg/C to 125/spl deg/C), and J Standard 020 Revision A Level 3 Moisture Sensitivity Preconditioning followed by reliability testing. Samples Cured using a second reflow pass are compared to baseline samples Cured in a standard batch oven based on the underfill manufacturer's recommended Cure schedule. Results from the processing of these new materials have shown a greatly reduced flow time from earlier generation underfill materials as all of these materials had flow times of less than 30 s under 5-mm test die. Through differential scanning calorimetry analysis, it was shown that materials requiring less than 8 min to Cure exhibited at least 95% conversion (percentage of material Cured) through the modified second side renew profile. Some of these commercial underfills have also passed J Standard 020 Revision A Level 3 Moisture Sensitivity testing. Specifically in this paper, the flip chip processing, underfill processing, moisture preconditioning, and preconditioning failure modes are presented.

P.n. Houston - One of the best experts on this subject based on the ideXlab platform.

  • Flux-underfill compatibility and failure mode analysis in high yield flip chip processing
    27th Annual IEEE SEMI International Electronics Manufacturing Technology Symposium, 2002
    Co-Authors: P.n. Houston, D.f. Baldwin, W.m. Tsai
    Abstract:

    The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, Snap Cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to evaluate the reliability of each flux-underfill material system. The failure modes, specifically underfill delamination, solder fatigue, and die cracking, are identified and analyzed. The correlation among process manufacturing defects, failure modes, and long-term reliability are determined. Understanding these failure modes will further enable and facilitate the implementation of low cost, high yield flip chip processing in standard surface mount technology.

  • processing and reliability of fast flow Snap Cure underfills part i processing and moisture sensitivity
    IEEE Transactions on Electronics Packaging Manufacturing, 2000
    Co-Authors: D.f. Baldwin, P.n. Houston, M. Deladisma, L.n. Crane, M. Konarski
    Abstract:

    This series of articles studies the processing, moisture sensitivity, reliability, and failure mode analysis of a number of commercial fast-flow, Snap-Cure underfill materials. It includes data on process analysis, processing times, and reliability of the test vehicles in air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C), liquid to liquid thermal shock (-55/spl deg/C to 125/spl deg/C), and J Standard 020 Revision A Level 3 Moisture Sensitivity Preconditioning followed by reliability testing. Samples Cured using a second reflow pass are compared to baseline samples Cured in a standard batch oven based on the underfill manufacturer's recommended Cure schedule. Results from the processing of these new materials have shown a greatly reduced flow time from earlier generation underfill materials as all of these materials had flow times of less than 30 s under 5-mm test die. Through differential scanning calorimetry analysis, it was shown that materials requiring less than 8 min to Cure exhibited at least 95% conversion (percentage of material Cured) through the modified second side renew profile. Some of these commercial underfills have also passed J Standard 020 Revision A Level 3 Moisture Sensitivity testing. Specifically in this paper, the flip chip processing, underfill processing, moisture preconditioning, and preconditioning failure modes are presented.

  • Processing and reliability of fast-flow, Snap-Cure underfills. I. Processing and moisture sensitivity
    IEEE Transactions on Electronics Packaging Manufacturing, 2000
    Co-Authors: D.f. Baldwin, P.n. Houston, M. Deladisma, L.n. Crane, M. Konarski
    Abstract:

    This series of articles studies the processing, moisture sensitivity, reliability, and failure mode analysis of a number of commercial fast-flow, Snap-Cure underfill materials. It includes data on process analysis, processing times, and reliability of the test vehicles in air-to-air thermal cycling (-55/spl deg/C to 125/spl deg/C), liquid to liquid thermal shock (-55/spl deg/C to 125/spl deg/C), and J Standard 020 Revision A Level 3 Moisture Sensitivity Preconditioning followed by reliability testing. Samples Cured using a second reflow pass are compared to baseline samples Cured in a standard batch oven based on the underfill manufacturer's recommended Cure schedule. Results from the processing of these new materials have shown a greatly reduced flow time from earlier generation underfill materials as all of these materials had flow times of less than 30 s under 5-mm test die. Through differential scanning calorimetry analysis, it was shown that materials requiring less than 8 min to Cure exhibited at least 95% conversion (percentage of material Cured) through the modified second side renew profile. Some of these commercial underfills have also passed J Standard 020 Revision A Level 3 Moisture Sensitivity testing. Specifically in this paper, the flip chip processing, underfill processing, moisture preconditioning, and preconditioning failure modes are presented.

  • Flux-underfill compatibility and failure mode analysis in high yield flip chip processing
    Twenty Sixth IEEE CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146), 2000
    Co-Authors: W.m. Tsai, P.n. Houston, D.f. Baldwin
    Abstract:

    The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, Snap Cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to evaluate the reliability of each flux-underfill material system. The failure modes, specifically underfill delamination, solder fatigue, and die cracking, are identified and analyzed. The correlation between process manufacturing defects, failure modes, and long-term reliability are determined. Understanding these failure modes will further enable and facilitate the implementation of low cost, high yield flip chip processing in standard surface mount technology.

  • Low cost flip chip processing and reliability of fast-flow, Snap-Cure underfills
    1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299), 1999
    Co-Authors: P.n. Houston, D.f. Baldwin, M. Deladisma, L.n. Crane, M. Konarski
    Abstract:

    Flip chip technology is finding increasing applications in the electronics manufacturing and packaging industries and is projected to grow at a 30-40% rate into the next decade. Development of new material systems will enable this growth provided they reduce manufacturing time and enhance reliability. Among these new materials are fast-flow, Snap-Cure underfills. These underfills can significantly decrease manufacturing costs by eliminating excessive underfill flow times and lengthy dedicated Cure cycles. This is especially true in double sided board assembly where Snap-Cure underfills can be Cured during the soak stage of a typical second side reflow cycle while the reflow spike forms the second side interconnects and also provides additional curing. This work presents a study of fast-flow, Snap-Cure underfill materials and includes data on the reliability in air to air thermal cycling (-55/spl deg/C to 125/spl deg/C) and JEDEC Level 3 Moisture Sensitivity Preconditioning prior to thermal cycling of FCOB test vehicles. Samples Cured using a second reflow pass are compared to baseline samples Snap-Cured in a standard batch oven at the underfill manufacturers' recommended Cure schedule. The goal of this work is to determine the performance of fast-flow, Snap-Cure underfills in the context of low cost flip chip processing using second side reflow for underfill Cure. The approach evaluates commercial fast-flow, Snap-Cure underfills with respect to JEDEC Level 3 Moisture Sensitivity Testing and air to air thermal cycling both with and without the preconditioning.

C.p. Wong - One of the best experts on this subject based on the ideXlab platform.

  • Chip scale Polymer Stud Grid Array packaging and reliability based on low cost flip Chip processing
    2020
    Co-Authors: C.s. Paydenkar, D.f. Baldwin, S. Sitaraman, C.p. Wong
    Abstract:

    The Polymer Stud Grid Array (PSGA ) package is a new and unique type of area array chip package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This package was designed and manufactured in response to a demand for low cost, high pin density packages. This paper focuses on two key elements to developing market share for PSGA technology which are: 1) developing high throughput flip chip assembly process technology for CSP-PSGA configurations using existing Surface Mount Technology (SMT) 2) assessing the reliability of assembled flip chip PSGA modules. The interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill material, and flip chip process technology, The underfill materials selected for evaluation are no-flow reflowable, fast flow Snap Cure encapsulants, and high reliability underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability data accumulated during liquid to liquid thermal cycling (-55°C to 125°C) of the assembled Chip Scaled Packages (CSPs).

  • Chip scale polymer stud grid array packaging and reliability based on low cost flip chip processing
    2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070), 2000
    Co-Authors: C.s. Paydenkar, D.f. Baldwin, S. Sitaraman, C.p. Wong, B.j. Lewis
    Abstract:

    The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential. This package was designed and manufactured in response to a demand for low cost, moderate pin density packages. This paper focuses on two key elements of PSGA technology which are: (1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT), and (2) qualifying the reliability performance of flip chip PSGA modules. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow Snap Cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability based on liquid to liquid thermal cycling (-55/spl deg/C to 125/spl deg/C) of the assembled PSGA Chip Scale Packages (CSPs).