The Experts below are selected from a list of 2775 Experts worldwide ranked by ideXlab platform
N G Durdle - One of the best experts on this subject based on the ideXlab platform.
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Sobel Edge Detection processor for a real time volume rendering system
International Symposium on Circuits and Systems, 2004Co-Authors: N Kazakova, Martin Margala, N G DurdleAbstract:This paper describes a novel fast and low-power Sobel Edge Detection processor targeted for image processing and volume rendering applications. The Sobel processor was built as a part of the real-time shear-warp factorization volume rendering system to compute a gradient. Sobel operator processor was designed and implemented in 0.18 /spl mu/m CMOS technology. Optimizations made at the mathematical model led to a simple regular architecture. High speed and low power consumption were achieved due to implementation of pipelining and parallelism at the components level. Employing the non-full swing CPL to design the Sobel processor sub-components reduced the power-delay product up to 40%. Simulation results showed that processor achieved the worst-case delay time of 4.61 ns and dissipates an average of 8.24 mW at 1.8 V and 200 MHz.
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ISCAS (2) - Sobel Edge Detection processor for a real-time volume rendering system
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: N Kazakova, Martin Margala, N G DurdleAbstract:This paper describes a novel fast and low-power Sobel Edge Detection processor targeted for image processing and volume rendering applications. The Sobel processor was built as a part of the real-time shear-warp factorization volume rendering system to compute a gradient. Sobel operator processor was designed and implemented in 0.18 /spl mu/m CMOS technology. Optimizations made at the mathematical model led to a simple regular architecture. High speed and low power consumption were achieved due to implementation of pipelining and parallelism at the components level. Employing the non-full swing CPL to design the Sobel processor sub-components reduced the power-delay product up to 40%. Simulation results showed that processor achieved the worst-case delay time of 4.61 ns and dissipates an average of 8.24 mW at 1.8 V and 200 MHz.
Guanglong Wang - One of the best experts on this subject based on the ideXlab platform.
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realization of real time Sobel adaptive threshold Edge Detection system based on fpga
International Conference on Information and Automation, 2015Co-Authors: Jie Tian, Guanglong WangAbstract:The Edge Detection system is an important part of intelligent vehicles. An adaptive threshold Edge Detection system is proposed for traditional Sobel Edge Detection system cannot satisfy the demand of accuracy. The Detection system includes of CMOS image sensor, FPGA, DDR2 and VGA etc. The real-time performance is good by aid of high-performance Cyclone IV GX series FPGA and DDR2. The experiment shows that the Sobel Edge Detection algorithm based on adaptive threshold can be realized on FPGA. And the system has the characteristics of high accuracy and excellent real-time performance.
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ICIA - Realization of real-time Sobel adaptive threshold Edge Detection system based on FPGA
2015 IEEE International Conference on Information and Automation, 2015Co-Authors: Jie Tian, Guanglong WangAbstract:The Edge Detection system is an important part of intelligent vehicles. An adaptive threshold Edge Detection system is proposed for traditional Sobel Edge Detection system cannot satisfy the demand of accuracy. The Detection system includes of CMOS image sensor, FPGA, DDR2 and VGA etc. The real-time performance is good by aid of high-performance Cyclone IV GX series FPGA and DDR2. The experiment shows that the Sobel Edge Detection algorithm based on adaptive threshold can be realized on FPGA. And the system has the characteristics of high accuracy and excellent real-time performance.
Srikanth Neelam - One of the best experts on this subject based on the ideXlab platform.
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iSES - Zynq FPGA Based System Design for Video Surveillance with Sobel Edge Detection
2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018Co-Authors: Sagar Eetha, Sonali Agarwal, Srikanth NeelamAbstract:Advancements in semiconductor domain gave way to realize numerous applications in Video Surveillance using Computer vision and Deep learning, Video Surveillances in Industrial automation, Security, ADAS, Live traffic analysis etc. through image understanding improves efficiency. Image understanding requires input data with high precision which is dependent on Image resolution and location of camera. The data of interest can be thermal image or live feed coming for various sensors. Composite(CVBS) is a popular video interface capable of streaming upto HD(1920x1080) quality. Unlike high speed serial interfaces like HDMI/MIPI CSI, Analog composite video interface is a single wire standard supporting longer distances. Image understanding requires Edge Detection and classification for further processing. Sobel filter is one the most used Edge Detection filter which can be embedded into live stream. This paper proposes Zynq FPGA based system design for video surveillance with Sobel Edge Detection, where the input Composite video decoded (Analog CVBS input to YCbCr digital output), processed in HW and streamed to HDMI display simultaneously storing in SD memory for later processing. The HW design is scalable for resolutions from VGA to Full HD for 60fps and 4K for 24fps. The system is built on Xilinx ZC702 platform and TVP5146 to showcase the functional path.
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Zynq FPGA Based System Design for Video Surveillance with Sobel Edge Detection
2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018Co-Authors: Sagar Eetha, Sonali Agrawal, Srikanth NeelamAbstract:Advancements in semiconductor domain gave way to realize numerous applications in Video Surveillance using Computer vision and Deep learning, Video Surveillances in Industrial automation, Security, ADAS, Live traffic analysis etc. through image understanding improves efficiency. Image understanding requires input data with high precision which is dependent on Image resolution and location of camera. The data of interest can be thermal image or live feed coming for various sensors. Composite(CVBS) is a popular video interface capable of streaming upto HD(1920x1080) quality. Unlike high speed serial interfaces like HDMI/MIPI CSI, Analog composite video interface is a single wire standard supporting longer distances. Image understanding requires Edge Detection and classification for further processing. Sobel filter is one the most used Edge Detection filter which can be embedded into live stream. This paper proposes Zynq FPGA based system design for video surveillance with Sobel Edge Detection, where the input Composite video decoded (Analog CVBS input to YCbCr digital output), processed in HW and streamed to HDMI display simultaneously storing in SD memory for later processing. The HW design is scalable for resolutions from VGA to Full HD for 60fps and 4K for 24fps. The system is built on Xilinx ZC702 platform and TVP5146 to showcase the functional path.
N Kazakova - One of the best experts on this subject based on the ideXlab platform.
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Sobel Edge Detection processor for a real time volume rendering system
International Symposium on Circuits and Systems, 2004Co-Authors: N Kazakova, Martin Margala, N G DurdleAbstract:This paper describes a novel fast and low-power Sobel Edge Detection processor targeted for image processing and volume rendering applications. The Sobel processor was built as a part of the real-time shear-warp factorization volume rendering system to compute a gradient. Sobel operator processor was designed and implemented in 0.18 /spl mu/m CMOS technology. Optimizations made at the mathematical model led to a simple regular architecture. High speed and low power consumption were achieved due to implementation of pipelining and parallelism at the components level. Employing the non-full swing CPL to design the Sobel processor sub-components reduced the power-delay product up to 40%. Simulation results showed that processor achieved the worst-case delay time of 4.61 ns and dissipates an average of 8.24 mW at 1.8 V and 200 MHz.
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ISCAS (2) - Sobel Edge Detection processor for a real-time volume rendering system
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: N Kazakova, Martin Margala, N G DurdleAbstract:This paper describes a novel fast and low-power Sobel Edge Detection processor targeted for image processing and volume rendering applications. The Sobel processor was built as a part of the real-time shear-warp factorization volume rendering system to compute a gradient. Sobel operator processor was designed and implemented in 0.18 /spl mu/m CMOS technology. Optimizations made at the mathematical model led to a simple regular architecture. High speed and low power consumption were achieved due to implementation of pipelining and parallelism at the components level. Employing the non-full swing CPL to design the Sobel processor sub-components reduced the power-delay product up to 40%. Simulation results showed that processor achieved the worst-case delay time of 4.61 ns and dissipates an average of 8.24 mW at 1.8 V and 200 MHz.
Mohamed Atri - One of the best experts on this subject based on the ideXlab platform.
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Sobel Edge Detection system design and integration on an fpga based hd video streaming architecture
Intelligent Decision Technologies, 2016Co-Authors: Abdelkader Ben Amara, Edwige Pissaloux, Mohamed AtriAbstract:Complex image processing algorithms (e.g. Sobel Edge Detection) combined with higher resolution video streaming, are so computationally and put bigger demands on processing power. Unlike the software solutions, parallel solutions satisfy well these algorithms' performance, but using a programmable logic such as FPGA's can provide us more. Driven by the rapid technological advances, today it's possible to combine a high-speed CPU and an FPGA technology on a single system on Chip (SoC), such as the Xilinx Zynq 7000 series. In this paper, we present a HD video streaming architecture and a Sobel Edge Detection IP core design and implementation using a high-level synthesis workflow. A HD video with a 1080p resolution streamed from a laptop HDMI interface. The processed videos were displayed by the use of a monitor. For implementation, we used a Digilent ZYBO Zynq ZC7010 based platform and our experimental results will be compared with an NVIDIA M840 GPU.
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IDT - Sobel Edge Detection system design and integration on an FPGA based HD video streaming architecture
2016 11th International Design & Test Symposium (IDT), 2016Co-Authors: Abdelkader Ben Amara, Edwige Pissaloux, Mohamed AtriAbstract:Complex image processing algorithms (e.g. Sobel Edge Detection) combined with higher resolution video streaming, are so computationally and put bigger demands on processing power. Unlike the software solutions, parallel solutions satisfy well these algorithms' performance, but using a programmable logic such as FPGA's can provide us more. Driven by the rapid technological advances, today it's possible to combine a high-speed CPU and an FPGA technology on a single system on Chip (SoC), such as the Xilinx Zynq 7000 series. In this paper, we present a HD video streaming architecture and a Sobel Edge Detection IP core design and implementation using a high-level synthesis workflow. A HD video with a 1080p resolution streamed from a laptop HDMI interface. The processed videos were displayed by the use of a monitor. For implementation, we used a Digilent ZYBO Zynq ZC7010 based platform and our experimental results will be compared with an NVIDIA M840 GPU.
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Efficient implementation of Sobel Edge Detection algorithm on CPU, GPU and FPGA
International Journal of Advanced Media and Communication, 2014Co-Authors: Marwa Chouchene, Mohamed Atri, Fatma Ezahra Sayadi, Yahia Said, Rached TourkiAbstract:Many applications in image processing have high degrees of inherent parallelism and are thus good candidates for parallel implementation. In fact, programming tools for field programmable gate array FPGA, SIMD instructions on CPU and a large number of cores on graphic processor unit GPU have been developed, but it is still difficult to achieve high performance on these platforms. This paper analyses the distinct features of compute unified device architecture CUDA GPU and summarises the general program mode of CUDA. Furthermore, we present three different implementations of Sobel Edge Detection on CPU, FPGA and GPU. Tested image data are also used in these hardware platforms to compare computational efficiency of CPU, GPU and FPGA.
