The Experts below are selected from a list of 324 Experts worldwide ranked by ideXlab platform
Jyh-hwa Tzou - One of the best experts on this subject based on the ideXlab platform.
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Rapid tooling for automated desktop manufacturing
30th Annual Conference of IEEE Industrial Electronics Society 2004. IECON 2004, 2004Co-Authors: Cheng Lung Chang, Zhong Hong Huang, Jyh-hwa TzouAbstract:A new rapid tooling (RT) system based on pre-placed metallic powder has been proposed. A 500 W Nd-YAG laser, a pre-placed powder mechanism, a linear planar motor based working table, and PC-based controller are incorporated for the hardware architecture. In this research, we propose a Software Technique that includes slicing with bucket sorting, direct slicing, and tool path generation algorithms. The slicing method provides the direct slicing of the CAD model in IGES geometric format to improve the accuracy of desired part. Effort was attempted to find out the better parameters of laser cladding using single clad and cladding layer Techniques. The process of the proposed system involves path control, laser cladding of layer by layer, milling, and finishing. Based on the investigation, some metallic components were fabricated.
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The development of a direct metallic rapid prototyping system
IEEE International Conference on Robotics and Automation 2004. Proceedings. ICRA '04. 2004, 2004Co-Authors: Chun-ching Chen, Jyh-hwa TzouAbstract:Rapid tooling (RT) refers to the rapid creation of molds in much the same way as rapid prototyping, which means the rapid creation of models. Rapid prototyping is a method that offers both designers and manufacturers some advantages such as time compression and cost reduction. Rapid tooling has become more important because of the requirement of rapid manufacturing. Rapid tooling can be used to produce temporary mold, even permanent mold in mass production. Rapid tooling makes more benefit from design stage to mass production. The objective of This work is to develop a metallic rapid prototyping system and form a complete set of important parameters of laser cladding. The Software Technique includes slicing algorithm with bucket sorting and tool path generation algorithm. The hardware architecture includes 500 W Nd-YAG laser, metallic powder feeder, coaxial nozzle, shielding gas (Ar) supply system, CNC milling system and linear planar motor based working table. The system controller is a PC-based control system, which includes 3-axis AC servo motor driver and I/O control card. The system control Software is written by Visual Basic language. The prototype system has been constructed and demonstrated.
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Advanced rapid prototyping manufacturing system for E-automation
Proceedings 2003 IEEE ASME International Conference on Advanced Intelligent Mechatronics (AIM 2003), 2003Co-Authors: Jyh-hwa TzouAbstract:Rapid prototyping Technique dramatically speeds up design and manufacturing processes and substantially reduces the cost. With the highly advanced network technologies, many different Software and hardware systems can be integrated as a distributed platform to provide more services, solve more complicated problems, and achieve better performance. We build a distributed Web platform on Internet using CORBA and some real-time technologies to effectively utilize various RP resources running on Linux, Solaris, or Microsoft Windows platforms. Users can design, simulate, and manufacture prototypes through a browser interface. Another objective of this paper is to develop a thermal extrusion based RP system which is equipped with a linear 2D planar motor. The RP Software Technique includes slicing, tool path and motion code generation. This paper also presents a new adaptive slicing algorithm, the 3D CAD model can be sliced with different thickness automatically by comparing the contour circumference or the center of gravity of the contour with those of the adjacent layer. By the experimental results, the proposed RP system can produce good quality RP parts.
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Investigation of a linear 2-D planar motor based rapid tooling system
Proceedings 2002 IEEE International Conference on Robotics and Automation (Cat. No.02CH37292), 2002Co-Authors: Jyh-hwa TzouAbstract:Rapid prototyping (RP) has been widely known as being able to fabricate 3-D objects with complex geometric shapes. Rapid tooling has become more important because of the requirement of rapid manufacture. Rapid tooling can be used to produce a temporary mold, even a permanent mold in mass production. The objective of the paper is to develop a rapid tooling system. The Software Technique includes a slicing algorithm and tool path generation algorithm. The hardware architecture includes a 500 W Nd:YAG laser, metallic powder feeder, substrate preheat system, shielding gas (N/sub 2/) supply system, CNC milling system and linear planar motor based working table. The system controller is a PC-based control system which includes 4-axis DSP motion control and an I/O control card. The system control Software is written in Visual Basic language. The experimental result shows that the linear 2-D planar motor based X-Y table has fast response and can make an accurate tool path.
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The development of a thermal extrusion based rapid prototyping mechatronics system
IEEE 2002 28th Annual Conference of the Industrial Electronics Society. IECON 02, 2002Co-Authors: Jyh-hwa Tzou, Cheng-yi Hsieh, Hsiu-hung ChouAbstract:The rapid prototyping (RP) technology can greatly reduce the production cycle time and tremendously contribute to quality. The objective of this paper is to develop a thermal extrusion based RP mechatronics system which is equipped with a linear 2D planar motor. The RP material is wax. The XYZ table is controlled by a PC based multi-axis DSP motion control card. The RP material flow rate of thermal extrusion head is controlled by a PC based D/A card. The RP Software Technique includes uniform slicing, adaptive slicing, tool path and motion code generation. Based on the experimental results, the proposed RP mechatronics system can produce good quality RP parts.
Luca Benini - One of the best experts on this subject based on the ideXlab platform.
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GPUguard: Towards supporting a predictable execution model for heterogeneous SoC
Design Automation & Test in Europe Conference & Exhibition (DATE) 2017, 2017Co-Authors: Björn Forsberg, Andrea Marongiu, Luca BeniniAbstract:The deployment of real-time workloads on commercial off-the-shelf (COTS) hardware is attractive, as it reduces the cost and time-to-market of new products. Most modern high-end embedded SoCs rely on a heterogeneous design, coupling a general-purpose multi-core CPU to a massively parallel accelerator, typically a programmable GPU, sharing a single global DRAM. However, because of non-predictable hardware arbiters designed to maximize average or peak performance, it is very difficult to provide timing guarantees on such systems. In this work we present our ongoing work on GPUguard, a Software Technique that predictably arbitrates main memory usage in heterogeneous SoCs. A prototype implementation for the NVIDIA Tegra TX1 SoC shows that GPUguard is able to reduce the adverse effects of memory sharing, while retaining a high throughput on both the CPU and the accelerator.
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Aging-aware compiler-directed VLIW assignment for GPGPU architectures
2013 50th ACM EDAC IEEE Design Automation Conference (DAC), 2013Co-Authors: Abbas Rahimi, Luca Benini, Rajesh K. GuptaAbstract:Negative bias temperature instability (NBTI) adversely affects the reliability of a processor by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across functional units and instructions: some are affected more (hence less reliable) than others. This paper proposes a NBTI-aware compiler-directed very long instruction word (VLIW) assignment scheme that uniformly distributes the stress of instructions with the aim of minimizing aging of GPGPU architecture without any performance penalty. The proposed solution is an entirely Software Technique based on static workload characterization and online execution with NBTI monitoring that equalizes the expected lifetime of each processing element by regenerating aging-aware healthy kernels that respond to the specific health state of GPGPU. We demonstrate our approach on AMD Evergreen architecture where iso-throughput executions of the healthy kernels reduce NBTI-induced voltage threshold shift up to 49% (11%) compared to naïve kernel executions, with (without) architectural support for power-gating. The kernel adaption flow takes average of 13 millisecond on a typical host machine thus making it suitable for practical implementation.
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HePREM: A Predictable Execution Model for GPU-based Heterogeneous SoCs
IEEE Transactions on Computers, 1Co-Authors: Bjöern Forsberg, Luca Benini, Andrea MarongiuAbstract:The ever-increasing need for computational power in embedded devices has led to the adoption of heterogeneous SoCs combining a general purpose CPU with a data parallel accelerator. These systems rely on a shared main memory (DRAM), which makes them highly susceptible to memory interference. A promising Software Technique to counter such effects is the Predictable Execution Model (PREM). PREM ensures robustness to interference by separating programs into a sequence of memory and compute phases, and by enforcing a platform-level schedule where only a single processing subsystem is permitted to execute a memory phase at a time. This paper demonstrates for the first time how PREM can be applied to heterogeneous SoCs, based on a synchronization Technique for memory isolation between CPU and GPU plus a compiler to transform GPU kernels into PREM-compliant codes. For compute bound GPU workloads sharing the DRAM bandwidth 50/50 with the CPU we guarantee near-zero timing varibility at a performance loss of just 59%, which is one to two orders of magnitude smaller than the worst case we see for unmodified programs under memory interference.
Cha Seung Jun - One of the best experts on this subject based on the ideXlab platform.
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Novel speed and rotor position estimation strategy using a dual observer for low-resolution position sensors
IEEE Transactions on Power Electronics, 2009Co-Authors: Anno Yoo, Dong Cheol Lee, Seung-ki Sul, Cha Seung JunAbstract:Recently, high-performance AC motor drive technologies, including field-oriented control (FOC), have been widely used in home appliance products such as direct-drive drum washing machines. In low-cost AC machine drive systems, speed or position sensors with high resolution are not available due to high costs. Instead, a low-resolution sensor is installed to calculate the speed and rotor position. In the FOC, however, accurate rotor angle information is essential for high performance. In addition to the low resolution of the sensor, its accuracy is poor due to mechanical errors and signal processing. The inaccurate and delayed position information degrades the performance of current regulation and also increases torque ripples, which is the source of mechanical vibration and acoustic noise. In order to overcome this hardware problem, this study proposes a Software Technique based on a novel dual observer and a position sensor offset compensation strategy. The dual observer can estimate the rotor speed and position without time delay or bumps. Also, with the compensation algorithm for position sensor offset, the misaligned synchronous reference frame d- and q-axis can be corrected. Experimental results verify the effectiveness of the proposed method.
Kiyoshi Horii - One of the best experts on this subject based on the ideXlab platform.
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Visualization and Detection of Wall Shear Stress using Micro Shear Stress Sensor and Discrete Wavelet Analysis
Ieej Transactions on Sensors and Micromachines, 2000Co-Authors: Motoaki Kimura, Norimasa Miyagi, Yoshifuru Saito, Chih-ming Ho, Masahiro Takei, Kiyoshi HoriiAbstract:Shear stress stripe structure on the wall in turbulent boundary layer has been clearly visualized by a combination of a shear stress sensor using MEMS (Micro-Electro-Mechanical-Systems) and discrete wavelets transform. The MEMS shear stress micro chip is designed and fabricated by surface micro-machining technology, contributing to obtaining the time-space two dimensional shear stress data. One array of 25 micro shear stress sensors in the chip that covers a length of 7.5mm is used to measure the instantaneous spanwise distribution of the surface shear stress. The discrete wavelets transform is a Software Technique to decompose the frequency level with the time and space information of the wave form. In details, the structure in lower Reynolds number is shown clearly on lower frequency wavelets level, the structure in high Reynolds number is done clearly on higher frequency wavelets level. To visualize and detect the high shear stress area more clearly, the frequency levels are recomposed using the multiresolution filtering effect of wavelets transform. The experiments for the shear stress distribution were carried out on Re=8700 and 17400.
J.m.f. Moura - One of the best experts on this subject based on the ideXlab platform.
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Spiral: Joint Runtime and Energy Optimization of Linear Transforms
2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings, 2006Co-Authors: M. Telgarsky, J.m.f. MouraAbstract:There is much interest into joint runtime and energy optimization of implementations of signal processing algorithms. Applications in domains such as embedded computing, sensor networks, and mobile communications often require processing of signals under simultaneous runtime, energy and/or power constraints. Hence, in addition to runtime, power and energy are first-order design considerations for both hardware and Software developers in those domains. This paper studies the automatic generation of Software implementations of digital signal processing (DSP) transforms that are optimized with respect to both runtime and energy. We explore the impact of algorithm selection (a Software Technique) and voltage-frequency scaling (a hardware Technique) on the runtime and energy of computing fast linear transforms. We use SPIRAL, a code generation system, to enumerate automatically many alternative algorithms for the discrete Fourier transform. We measure the runtime and energy of these algorithms at different voltage-frequency settings of an Intel Pentium M microprocessor. We report experimental results supporting that algorithm selection and voltage-frequency scaling do achieve the following: (1) have large impact on the runtime and energy of computing the discrete Fourier transform on a microprocessor; and (2) enable the optimization of important joint runtime-energy objectives
