The Experts below are selected from a list of 126 Experts worldwide ranked by ideXlab platform
Hidetoshi Onodera - One of the best experts on this subject based on the ideXlab platform.
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bandwidth enhancement for high Speed Amplifier utilizing mutually coupled on chip inductors
International SoC Design Conference, 2011Co-Authors: Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi OnoderaAbstract:This paper discusses bandwidth enhancement technique for high Speed Amplifier. Inductive peaking is a common practice for bandwidth enhancement, however the area occupied by on-chip inductors is a heavy disadvantage. We utilize mutually coupled inductors for effective inductive peaking. A Laser-Diode (LD) driver for optical communication system is designed in a 0.18//m CMOS. Measurement results show that the mutually coupled inductor can achieve 16Gbps operation and 26% area reduction compared to conventional shunt peaking.
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ISOCC - Bandwidth enhancement for high Speed Amplifier utilizing mutually coupled on-chip inductors
2011 International SoC Design Conference, 2011Co-Authors: Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi OnoderaAbstract:This paper discusses bandwidth enhancement technique for high Speed Amplifier. Inductive peaking is a common practice for bandwidth enhancement, however the area occupied by on-chip inductors is a heavy disadvantage. We utilize mutually coupled inductors for effective inductive peaking. A Laser-Diode (LD) driver for optical communication system is designed in a 0.18//m CMOS. Measurement results show that the mutually coupled inductor can achieve 16Gbps operation and 26% area reduction compared to conventional shunt peaking.
D. Y. Kim - One of the best experts on this subject based on the ideXlab platform.
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Design of a New High Speed Amplifier Circuit for the Analog Subsystems
Analog Integrated Circuits and Signal Processing, 2002Co-Authors: S. I. Cho, J. H. Bang, D. Y. KimAbstract:A high Speed CMOS Amplifier circuit with a new architecture especially suited for analog subsystems and a simple high Speed CMOS comparator utilizing the proposed CMOS Amplifier circuit are presented. The proposed circuit is simulated using 0.35 μm process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended Amplifier. Design details and simulation results show that the newly designed CMOS Amplifier circuit and the high Speed CMOS comparator are applicable to high Speed analog subsystems, especially the flash A/D converter.
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The design of the high Speed Amplifier circuit for using in the analog subsystems
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 1Co-Authors: D. Y. Kim, O.s. Kwon, J. H. BangAbstract:A high-Speed CMOS Amplifier circuit has been designed and applied in a high-Speed simple CMOS comparator. The designed CMOS Amplifier circuit has a new architecture for use in high-Speed analog subsystem circuits. This architecture is composed of internal biasing circuits and a CMOS complementary gain stage and has improved gain and Speed characteristics. A high Speed simple CMOS comparator using an improved CMOS Amplifier circuit with a standard 1.5 mu m processing parameter has been designed. This circuit can be operated in a few nanoseconds. >
J. H. Bang - One of the best experts on this subject based on the ideXlab platform.
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Design of a New High Speed Amplifier Circuit for the Analog Subsystems
Analog Integrated Circuits and Signal Processing, 2002Co-Authors: S. I. Cho, J. H. Bang, D. Y. KimAbstract:A high Speed CMOS Amplifier circuit with a new architecture especially suited for analog subsystems and a simple high Speed CMOS comparator utilizing the proposed CMOS Amplifier circuit are presented. The proposed circuit is simulated using 0.35 μm process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended Amplifier. Design details and simulation results show that the newly designed CMOS Amplifier circuit and the high Speed CMOS comparator are applicable to high Speed analog subsystems, especially the flash A/D converter.
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The design of the high Speed Amplifier circuit for using in the analog subsystems
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 1Co-Authors: D. Y. Kim, O.s. Kwon, J. H. BangAbstract:A high-Speed CMOS Amplifier circuit has been designed and applied in a high-Speed simple CMOS comparator. The designed CMOS Amplifier circuit has a new architecture for use in high-Speed analog subsystem circuits. This architecture is composed of internal biasing circuits and a CMOS complementary gain stage and has improved gain and Speed characteristics. A high Speed simple CMOS comparator using an improved CMOS Amplifier circuit with a standard 1.5 mu m processing parameter has been designed. This circuit can be operated in a few nanoseconds. >
Cam Nguyen - One of the best experts on this subject based on the ideXlab platform.
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On the development of a compact sub-nanosecond tunable monocycle pulse transmitter for UWB applications
IEEE Transactions on Microwave Theory and Techniques, 2006Co-Authors: Jeongwoo Han, Cam NguyenAbstract:Development of a new sub-nanosecond monocycle pulse transmitter with tunable pulse duration for short-range low-power ultra-wideband radar and communication systems is presented along with detailed design and analysis. The developed pulse transmitter is simple, compact, and can be realized using planar or uniplanar integrated circuits. A novel RC coupling circuit along with a high driving current, provided by a high-Speed Amplifier and buffers, are used to obtain an increase in the output power. A decoupling circuit is implemented to reduce ringing on the monocycle pulse and provide necessary pulse clamping. Tuning of the output monocycle-pulse duration is achieved by using two distributed delay lines, coupled together by the decoupling network, each spatially loaded with antiparallel p-i-n diodes that are alternately switched on and off. Measurement results show tunable monocycle pulse durations in range of 0.4-1.2 ns, approximately corresponding to the operating frequency range of 0.15-3.7 GHz, and 200-400 mW of pulse peak power. The calculated and measured pulse durations also agree reasonably well
Akira Tsuchiya - One of the best experts on this subject based on the ideXlab platform.
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bandwidth enhancement for high Speed Amplifier utilizing mutually coupled on chip inductors
International SoC Design Conference, 2011Co-Authors: Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi OnoderaAbstract:This paper discusses bandwidth enhancement technique for high Speed Amplifier. Inductive peaking is a common practice for bandwidth enhancement, however the area occupied by on-chip inductors is a heavy disadvantage. We utilize mutually coupled inductors for effective inductive peaking. A Laser-Diode (LD) driver for optical communication system is designed in a 0.18//m CMOS. Measurement results show that the mutually coupled inductor can achieve 16Gbps operation and 26% area reduction compared to conventional shunt peaking.
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ISOCC - Bandwidth enhancement for high Speed Amplifier utilizing mutually coupled on-chip inductors
2011 International SoC Design Conference, 2011Co-Authors: Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi OnoderaAbstract:This paper discusses bandwidth enhancement technique for high Speed Amplifier. Inductive peaking is a common practice for bandwidth enhancement, however the area occupied by on-chip inductors is a heavy disadvantage. We utilize mutually coupled inductors for effective inductive peaking. A Laser-Diode (LD) driver for optical communication system is designed in a 0.18//m CMOS. Measurement results show that the mutually coupled inductor can achieve 16Gbps operation and 26% area reduction compared to conventional shunt peaking.