The Experts below are selected from a list of 150831 Experts worldwide ranked by ideXlab platform
Tuo-hung Hou - One of the best experts on this subject based on the ideXlab platform.
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3D resistive RAM cell design for high-density storage class Memory---a review
Science China Information Sciences, 2016Co-Authors: Boris Hudec, Chung-wei Hsu, I-ting Wang, Chen-hsi Lin, Weili Lai, Che-chia Chang, Karol Fröhlich, Taifang Wang, Tuo-hung HouAbstract:In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes---3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed Memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO$_{2}$-based filamentary 3D Vertical ReRAM as well as TaO$_{x}$/TiO$_{2 }$ bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
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Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
IEEE Transactions on Electron Devices, 2015Co-Authors: Jen-chieh Liu, Chung-wei Hsu, I-ting Wang, Tuo-hung HouAbstract:This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in Storage-Class Memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access Memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
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homogeneous barrier modulation of taox tio2 bilayers for ultra high endurance three dimensional storage class Memory
Nanotechnology, 2014Co-Authors: Chung-wei Hsu, I-ting Wang, Yufen Wang, Chiachen Wan, Chuntse Chou, Weili Lai, Yaojen Lee, Tuo-hung HouAbstract:Three-dimensional vertical resistive-switching random access Memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive Storage-Class Memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 103 with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 1015 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage Memory by exploiting a unique tradeoff between retention time and endurance.
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Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional Storage-Class Memory
Nanotechnology, 2014Co-Authors: Chung-wei Hsu, I-ting Wang, Yufen Wang, Chiachen Wan, Chuntse Chou, Weili Lai, Yaojen Lee, Tuo-hung HouAbstract:Three-dimensional vertical resistive-switching random access Memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive Storage-Class Memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 103 with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 1015 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage Memory by exploiting a unique tradeoff between retention time and endurance.
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Self-rectifying bipolar TaO x /TiO 2 RRAM with superior endurance over 10 12 cycles for 3D high-density Storage-Class Memory
2013Co-Authors: Chung-wei Hsu, I-ting Wang, Ming-chung Chiang, Wen-yueh Jang, Chen-hsi Lin, Tuo-hung HouAbstract:To satisfy strict requirements of Storage-Class Memory, a bipolar TaOx/TiO2 RRAM has been developed. Numerous highly desired features, including: (1) extremely high endurance over 1012 cycles, (2) forming free, (3) self compliance, (4) self rectification ratio up to 105 required for ultrahigh-density 3D vertical RRAM, (5) multiple-level-per-cell capability, (6) room-temperature process, and (7) fab-friendly materials, have been demonstrated simultaneously for the first time.
Ken Takeuchi - One of the best experts on this subject based on the ideXlab platform.
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Analysis on applicable error-correcting code strength of storage class Memory and NAND flash in hybrid storage
Japanese Journal of Applied Physics, 2018Co-Authors: Chihiro Matsui, Reika Kinoshita, Ken TakeuchiAbstract:A hybrid of storage class Memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra Memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one Memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.
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Application-oriented wear-leveling optimization of 3D TSV-integrated storage class Memory-based solid state drives
2018 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC), 2018Co-Authors: Masaru Nakanishi, Chihiro Matsui, Yusuke Sugiyama, Yutaka Adachi, Ken TakeuchiAbstract:Storage class memories (SCMs) are expected as next generation non-volatile Memory due to their high performance, high scalability and low energy consumption [1]. Since the SCM endurance is limited, wear-leveling is required. Wear-leveling is the function on SSD controller to distribute overwrite count each Memory cell and to avoid excessive overwrite to particular cells. However, frequent wear-leveling greatly affects the performance of SSDs. In this paper, the frequency of wear-leveling in SCM-based SSD is optimized for real world application. By optimizing frequency of wear-levering for each application, SCM-based SSD performance improves by 38.6% and energy consumption decreases by 18.0%, respectively. Moreover, energy consumption of SCM-based SSD is reduced by up to 82.8% by introducing through-silicon via (TSV) instead of bonding-wire.
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optimal Memory configuration analysis in tri hybrid solid state drives with storage class Memory and multi level cell triple level cell nand flash Memory
Japanese Journal of Applied Physics, 2017Co-Authors: Chihiro Matsui, Tomoaki Yamada, Yusuke Sugiyama, Yusuke Yamaga, Ken TakeuchiAbstract:This paper analyzes the best mix of memories in a tri-hybrid solid-state drive (SSD) with storage class Memory (SCM) and multi-level cell (MLC)/triple-level cell (TLC) NAND flash Memory. SCM is fast but its cost is high. Although MLC NAND flash Memory is slow, it is more cost effective than SCM. For further cost efficiency, TLC NAND flash Memory is denser and less expensive than MLC NAND flash. Performance of tri-hybrid SSD is evaluated in various Memory configurations. Moreover, the optimum Memory configuration is changed according to the application characteristics. If 10% cost increase is allowed compared to the MLC NAND flash only SSD, SCM/MLC NAND flash hybrid SSD provides the best performance with hot/random workload, whereas SCM/MLC/TLC NAND flash tri-hybrid SSD achieves the best for hot/sequential and cold/random workloads. In addition, it is possible to add long latency but low-cost SCM to the tri-hybrid SSD. As a result, tri-hybrid SSD with slow SCM achieves the best performance.
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Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory
Proceedings of the IEEE, 2017Co-Authors: Chihiro Matsui, Chao Sun, Ken TakeuchiAbstract:NAND flash Memory-based solid-state drives (SSDs) are increasingly being used in both consumer and enterprise storage markets, due to their superior performance over hard disk drives (HDDs) and continuous bit cost reductions. With multiple-level cell technology Memory device is capable of trading off the performance and endurance with bit density. The more bits per cell there are, the longer latency and shorter lifetime. On the other hand, the performance of such SSDs is limited due to NAND flash access speed as well as the need of garbage collection. Recently, storage class memories (SCMs) like resistive RAM (ReRAM) and phase change RAM (PRAM) have been developed to fill the bandwidth gap between DRAM and NAND flash Memory. SCMs are nonvolatile and byte addressable, which are much faster and durable than NAND flash. Therefore, with SCMs, the storage performance would be significantly improved. Hybrid SSDs are promising cost-efficient storage solutions. Various types of memories like single-level cell (SLC), multiple-level cell (MLC), triple-level cell (TLC) NAND flash memories, and SCMs create lots of opportunities for new system architectures and algorithms. In this paper, the architecture and algorithm design overview of three types of hybrid drives including MLC/TLC NAND flash hybrid, SCM/MLC NAND flash hybrid, and SCM/MLC/TLC NAND flash tri-hybrid are presented. From the evaluation results, hybrid drives demonstrate better performance, endurance, and power consumption, compared to the MLC NAND flash only SSD. Furthermore, the relationship between device reliability and performance of the SCM/NAND flash hybrid SSD has been understood at a system level. There is a tradeoff between acceptable bit error rate of SCM and NAND flash. In addition, the decoding latency of SCM affects the performance of hybrid SSD more than that of NAND flash.
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design guidelines of storage class Memory flash hybrid solid state drive considering system architecture algorithm and workload characteristic
IEEE Transactions on Consumer Electronics, 2016Co-Authors: Shun Okamoto, Tomoaki Yamada, Shogo Hachiya, Ken TakeuchiAbstract:Solid-state drives (SSDs), composed of NAND flash memories, are replacing hard disk drives (HDDs) rapidly. In addition, storage class memories (SCMs) bridge the bandwidth gap between DRAM and NAND flash, thus introducing SCM to SSD further improves the solid storage performance. Different from schemes that use SCM to store file system metadata or logical to physical mapping tables, two architectures 1) use SCM as a write-back non-volatile Memory (NVM) based cache, 2) use SCM as a storage device are presented in this paper. Since SCM chip latency varies due to Memory device and circuit design, three SSD data management algorithms are evaluated under five SCM chip design scenarios to provide useful design guidelines of SCM/NAND flash hybrid SSD. SCM interface and capacity requirement are also analyzed. From the experimental results, less than 10% of the SCM/NAND flash capacity ratio is enough for SCM chips with 500 ns read and 5 μs write latency to boost NAND flash-only SSD speed by over 10 times when workloads own high IO skew1.
Chung-wei Hsu - One of the best experts on this subject based on the ideXlab platform.
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3D resistive RAM cell design for high-density storage class Memory---a review
Science China Information Sciences, 2016Co-Authors: Boris Hudec, Chung-wei Hsu, I-ting Wang, Chen-hsi Lin, Weili Lai, Che-chia Chang, Karol Fröhlich, Taifang Wang, Tuo-hung HouAbstract:In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes---3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed Memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO$_{2}$-based filamentary 3D Vertical ReRAM as well as TaO$_{x}$/TiO$_{2 }$ bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
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Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
IEEE Transactions on Electron Devices, 2015Co-Authors: Jen-chieh Liu, Chung-wei Hsu, I-ting Wang, Tuo-hung HouAbstract:This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in Storage-Class Memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access Memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
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homogeneous barrier modulation of taox tio2 bilayers for ultra high endurance three dimensional storage class Memory
Nanotechnology, 2014Co-Authors: Chung-wei Hsu, I-ting Wang, Yufen Wang, Chiachen Wan, Chuntse Chou, Weili Lai, Yaojen Lee, Tuo-hung HouAbstract:Three-dimensional vertical resistive-switching random access Memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive Storage-Class Memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 103 with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 1015 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage Memory by exploiting a unique tradeoff between retention time and endurance.
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Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional Storage-Class Memory
Nanotechnology, 2014Co-Authors: Chung-wei Hsu, I-ting Wang, Yufen Wang, Chiachen Wan, Chuntse Chou, Weili Lai, Yaojen Lee, Tuo-hung HouAbstract:Three-dimensional vertical resistive-switching random access Memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive Storage-Class Memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 103 with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 1015 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage Memory by exploiting a unique tradeoff between retention time and endurance.
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Self-rectifying bipolar TaO x /TiO 2 RRAM with superior endurance over 10 12 cycles for 3D high-density Storage-Class Memory
2013Co-Authors: Chung-wei Hsu, I-ting Wang, Ming-chung Chiang, Wen-yueh Jang, Chen-hsi Lin, Tuo-hung HouAbstract:To satisfy strict requirements of Storage-Class Memory, a bipolar TaOx/TiO2 RRAM has been developed. Numerous highly desired features, including: (1) extremely high endurance over 1012 cycles, (2) forming free, (3) self compliance, (4) self rectification ratio up to 105 required for ultrahigh-density 3D vertical RRAM, (5) multiple-level-per-cell capability, (6) room-temperature process, and (7) fab-friendly materials, have been demonstrated simultaneously for the first time.
I-ting Wang - One of the best experts on this subject based on the ideXlab platform.
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Three dimensional integration of ReRAMs
2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO), 2018Co-Authors: Boris Hudec, I-ting Wang, Che-chia Chang, Karol Fröhlich, Tuo-hung HauAbstract:Storage-Class Memory, non-volatile, ultra-dense and lightning fast, may enable Memory-driven computing to revolutionize the current architectures leading to an on-chip processing of vast amount of data. 3D vertical resistive random access Memory (ReRAM) is a hot candidate for Storage-Class Memory. In this talk we review current state-of-the-art works which offer promising solutions, utilizing either filamentary or non-filamentary ReRAM designs, including our own. We will discuss the pros and cons of different approaches and summarize the open problems, drawing possible solutions.
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3D resistive RAM cell design for high-density storage class Memory---a review
Science China Information Sciences, 2016Co-Authors: Boris Hudec, Chung-wei Hsu, I-ting Wang, Chen-hsi Lin, Weili Lai, Che-chia Chang, Karol Fröhlich, Taifang Wang, Tuo-hung HouAbstract:In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes---3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed Memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO$_{2}$-based filamentary 3D Vertical ReRAM as well as TaO$_{x}$/TiO$_{2 }$ bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
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Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
IEEE Transactions on Electron Devices, 2015Co-Authors: Jen-chieh Liu, Chung-wei Hsu, I-ting Wang, Tuo-hung HouAbstract:This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in Storage-Class Memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access Memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
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homogeneous barrier modulation of taox tio2 bilayers for ultra high endurance three dimensional storage class Memory
Nanotechnology, 2014Co-Authors: Chung-wei Hsu, I-ting Wang, Yufen Wang, Chiachen Wan, Chuntse Chou, Weili Lai, Yaojen Lee, Tuo-hung HouAbstract:Three-dimensional vertical resistive-switching random access Memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive Storage-Class Memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 103 with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 1015 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage Memory by exploiting a unique tradeoff between retention time and endurance.
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Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional Storage-Class Memory
Nanotechnology, 2014Co-Authors: Chung-wei Hsu, I-ting Wang, Yufen Wang, Chiachen Wan, Chuntse Chou, Weili Lai, Yaojen Lee, Tuo-hung HouAbstract:Three-dimensional vertical resistive-switching random access Memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive Storage-Class Memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 103 with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 1015 cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage Memory by exploiting a unique tradeoff between retention time and endurance.
Sungyong Park - One of the best experts on this subject based on the ideXlab platform.
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Understanding the performance of storage class Memory file systems in the NUMA architecture
Cluster Computing, 2019Co-Authors: Jangwoong Kim, Awais Khan, Youngjae Kim, Sungyong ParkAbstract:Recent developments in storage class Memory (SCM) such as PCM, MRAM, resistive RAM (RRAM), and spin-transfer torque (STT)-RAM have strengthened their leadership as storage media for Memory-based file systems. Traditional Linux Memory-based file systems such as Ramfs and Tmpfs utilize the Linux page cache as a file system. These file systems have unnecessary overheads when adopted for SCM file system. Therefore, we propose a new Memory-based file system using Memory Zone Partitioning called ZonFS , by extending the Linux Ramfs. In particular, we define a storage zone for SCM, modify the Ramfs to allocate a file system page from SCM. ZonFS avoids running Linux VM kernel codes such as (i) inserting pages allocated from SCM into the LRU list for VM page replacement and (ii) checking dirty pages for write-back to disk. Our extensive evaluations indicate that ZonFS has up to 9.1 and 14.1% higher I/O throughputs than native Ramfs and Tmpfs. Moreover, we also analyze performance behavior of ZonFS under the non-uniform Memory access architecture of SCMs on a 40 manycore machine with various configurations such as file sharing level and file stripping level. Our evaluations show that Memory controller contention and inter-node link congestion significantly affect the file system’s performance and scalability.
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zonfs a storage class Memory file system with Memory zone partitioning on linux
2017 IEEE 2nd International Workshops on Foundations and Applications of Self* Systems (FAS*W), 2017Co-Authors: Awais Khan, Sungyong ParkAbstract:Recent developments in storage class Memory such as PCM, MRAM, RRAM, and STT-RAM have strengthened their leadership as storage media for Memory-based file systems. Traditional Linux Memory-based file systems such as Ramfs and Tmpfs utilize the Linux page cache as a file system. These file systems, when adopted as a file system for SCM, have the following problems. First, current implementation of Ramfs and Tmpfs has no mechanism to explicitly allocate pages from specific Memory. Second, Memory pages allocated from SCM do not have to follow the Linux kernel's page allocation process exactly. This results in unnecessary performance overhead. To resolve the aforementioned challenges, we propose the development of ZonFS, a Memory-based file system using Memory Zone Partitioning. ZonFS is implemented by extending the Linux Ramfs. In particular, we defined a Memory zone for SCM, modified the Ramfs to allocate a file system page from SCM. ZonFS implementation avoids running unnecessary Linux VM codes such as (i) inserting a page allocated from SCM into the LRU list for VM page replacement and (ii) checking dirty pages for write back to disk. We also modified the Ramfs to allocate inode cache in SCM and eliminated the risk of inode cache loss in case of power failure. Extensive evaluation indicates that ZonFS has up to 9.1% and 13.8% higher I/O throughputs than native Ramfs and Tmpfs.
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FAS*W@SASO/ICCAC - ZonFS: A Storage Class Memory File System with Memory Zone Partitioning on Linux
2017 IEEE 2nd International Workshops on Foundations and Applications of Self* Systems (FAS*W), 2017Co-Authors: Jangwoong Kim, Awais Khan, Youngjae Kim, Jae Hoon Kim, Sungyong ParkAbstract:Recent developments in storage class Memory such as PCM, MRAM, RRAM, and STT-RAM have strengthened their leadership as storage media for Memory-based file systems. Traditional Linux Memory-based file systems such as Ramfs and Tmpfs utilize the Linux page cache as a file system. These file systems, when adopted as a file system for SCM, have the following problems. First, current implementation of Ramfs and Tmpfs has no mechanism to explicitly allocate pages from specific Memory. Second, Memory pages allocated from SCM do not have to follow the Linux kernel's page allocation process exactly. This results in unnecessary performance overhead. To resolve the aforementioned challenges, we propose the development of ZonFS, a Memory-based file system using Memory Zone Partitioning. ZonFS is implemented by extending the Linux Ramfs. In particular, we defined a Memory zone for SCM, modified the Ramfs to allocate a file system page from SCM. ZonFS implementation avoids running unnecessary Linux VM codes such as (i) inserting a page allocated from SCM into the LRU list for VM page replacement and (ii) checking dirty pages for write back to disk. We also modified the Ramfs to allocate inode cache in SCM and eliminated the risk of inode cache loss in case of power failure. Extensive evaluation indicates that ZonFS has up to 9.1% and 13.8% higher I/O throughputs than native Ramfs and Tmpfs.
