The Experts below are selected from a list of 39 Experts worldwide ranked by ideXlab platform
Tajana Rosing - One of the best experts on this subject based on the ideXlab platform.
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Low power data-aware STT-RAM based hybrid cache architecture
2016 17th International Symposium on Quality Electronic Design (ISQED), 2016Co-Authors: Mohsen Imani, Shruti Patil, Tajana RosingAbstract:Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient Memory. However, STT-RAM suffers from high write energy and latency, especially when writing `one' data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low-power 5T-SRAM structure which has high reliability for majority `one' data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT-RAM and SRAM partitions. We employed a write cache policy and a small Swap Memory to control data migration between cache partitions. Our evaluation on UltraSPARC-III processor shows that utilizing STT-RAM/6T-SRAM and STT-RAM/5T-SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM-based cache running SPEC CPU 2006 benchmarks.
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ISQED - Low power data-aware STT-RAM based hybrid cache architecture
2016 17th International Symposium on Quality Electronic Design (ISQED), 2016Co-Authors: Mohsen Imani, Shruti Patil, Tajana RosingAbstract:Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient Memory. However, STT-RAM suffers from high write energy and latency, especially when writing ‘one’ data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low-power 5T-SRAM structure which has high reliability for majority ‘one’ data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT-RAM and SRAM partitions. We employed a write cache policy and a small Swap Memory to control data migration between cache partitions. Our evaluation on UltraSPARC-III processor shows that utilizing STT-RAM/6T-SRAM and STT-RAM/5T-SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM-based cache running SPEC CPU 2006 benchmarks.
Mohsen Imani - One of the best experts on this subject based on the ideXlab platform.
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Low power data-aware STT-RAM based hybrid cache architecture
2016 17th International Symposium on Quality Electronic Design (ISQED), 2016Co-Authors: Mohsen Imani, Shruti Patil, Tajana RosingAbstract:Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient Memory. However, STT-RAM suffers from high write energy and latency, especially when writing `one' data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low-power 5T-SRAM structure which has high reliability for majority `one' data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT-RAM and SRAM partitions. We employed a write cache policy and a small Swap Memory to control data migration between cache partitions. Our evaluation on UltraSPARC-III processor shows that utilizing STT-RAM/6T-SRAM and STT-RAM/5T-SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM-based cache running SPEC CPU 2006 benchmarks.
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ISQED - Low power data-aware STT-RAM based hybrid cache architecture
2016 17th International Symposium on Quality Electronic Design (ISQED), 2016Co-Authors: Mohsen Imani, Shruti Patil, Tajana RosingAbstract:Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient Memory. However, STT-RAM suffers from high write energy and latency, especially when writing ‘one’ data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low-power 5T-SRAM structure which has high reliability for majority ‘one’ data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT-RAM and SRAM partitions. We employed a write cache policy and a small Swap Memory to control data migration between cache partitions. Our evaluation on UltraSPARC-III processor shows that utilizing STT-RAM/6T-SRAM and STT-RAM/5T-SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM-based cache running SPEC CPU 2006 benchmarks.
Shruti Patil - One of the best experts on this subject based on the ideXlab platform.
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Low power data-aware STT-RAM based hybrid cache architecture
2016 17th International Symposium on Quality Electronic Design (ISQED), 2016Co-Authors: Mohsen Imani, Shruti Patil, Tajana RosingAbstract:Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient Memory. However, STT-RAM suffers from high write energy and latency, especially when writing `one' data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low-power 5T-SRAM structure which has high reliability for majority `one' data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT-RAM and SRAM partitions. We employed a write cache policy and a small Swap Memory to control data migration between cache partitions. Our evaluation on UltraSPARC-III processor shows that utilizing STT-RAM/6T-SRAM and STT-RAM/5T-SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM-based cache running SPEC CPU 2006 benchmarks.
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ISQED - Low power data-aware STT-RAM based hybrid cache architecture
2016 17th International Symposium on Quality Electronic Design (ISQED), 2016Co-Authors: Mohsen Imani, Shruti Patil, Tajana RosingAbstract:Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient Memory. However, STT-RAM suffers from high write energy and latency, especially when writing ‘one’ data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based on their bit counts. To exploit the new resultant data distribution in the SRAM partition, we employ an asymmetric low-power 5T-SRAM structure which has high reliability for majority ‘one’ data. The proposed design significantly reduces the number of writes and hence dynamic energy in both STT-RAM and SRAM partitions. We employed a write cache policy and a small Swap Memory to control data migration between cache partitions. Our evaluation on UltraSPARC-III processor shows that utilizing STT-RAM/6T-SRAM and STT-RAM/5T-SRAM architectures for the L2 cache results in 42% and 53% energy efficiency, 9.3% and 9.1% performance improvement and 16.9% and 20.3% area efficiency respectively, with respect to SRAM-based cache running SPEC CPU 2006 benchmarks.
Paulo Maciel - One of the best experts on this subject based on the ideXlab platform.
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SMC - Experimental evaluation of software aging effects in the eucalyptus elastic block storage
2012 IEEE International Conference on Systems Man and Cybernetics (SMC), 2012Co-Authors: Rubens Matos, Jean Araujo, Vandi Alves, Paulo MacielAbstract:The need for reliability, availability and performance has increased in modern applications, which need to handle rapidly growing demands while providing uninterrupted service. Cloud computing systems fundamentally provide access to large pools of data and computational resources. Eucalyptus is a software framework used to implement private clouds and hybrid-style Infrastructure as a Service. It implements the API Amazon Web Service (AWS), allowing interoperability with other AWS-based services. Elastic block storage is a technology which provides flexible allocation of remote storage volumes to the virtual machines running in a cloud computing environment. This work investigates the software aging effects on the Eucalyptus framework, considering workloads composed of intensive requests for attaching remote storage volumes to virtual machines. The results evidenced problems that may be harmful to system dependability and its performance due to RAM Memory exhaustion and subsequent use of Swap Memory, besides high CPU utilization by the virtual machines and subsequent increase in the response time of applications running on the VMs.
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Experimental evaluation of software aging effects in the eucalyptus elastic block storage
2012 IEEE International Conference on Systems Man and Cybernetics (SMC), 2012Co-Authors: Rubens Matos, Jean Araujo, Vandi Alves, Paulo MacielAbstract:The need for reliability, availability and performance has increased in modern applications, which need to handle rapidly growing demands while providing uninterrupted service. Cloud computing systems fundamentally provide access to large pools of data and computational resources. Eucalyptus is a software framework used to implement private clouds and hybrid-style Infrastructure as a Service. It implements the API Amazon Web Service (AWS), allowing interoperability with other AWS-based services. Elastic block storage is a technology which provides flexible allocation of remote storage volumes to the virtual machines running in a cloud computing environment. This work investigates the software aging effects on the Eucalyptus framework, considering workloads composed of intensive requests for attaching remote storage volumes to virtual machines. The results evidenced problems that may be harmful to system dependability and its performance due to RAM Memory exhaustion and subsequent use of Swap Memory, besides high CPU utilization by the virtual machines and subsequent increase in the response time of applications running on the VMs.
Christopher Paolini - One of the best experts on this subject based on the ideXlab platform.
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ICPP Workshops - A Load Balancing Scheme for ebXML Registries
2010 39th International Conference on Parallel Processing Workshops, 2010Co-Authors: Sadhana Sahasrabudhe, Christopher PaoliniAbstract:Large scale Service Oriented Architecture (SOA) developments are becoming increasingly reliant on registry services that manage Web Services using taxonomic attributes. At present a registry stores a Web Services interface definition and protocol bindings in WSDL, along with one or more XML schema files that define the structure of a SOAP message exchanged between Web Services operations and client processes and other static metadata. During Web Service discovery an ebXML registry returns the access URI associated with the service binding to allow dynamic discovery and invocation. This usually restricts a calling process to a Web Service invocation on one host. This work explores a mechanism to manage service bindings for a Web Service that has been deployed across multiple hosts, such that, a URI returned by a registry can resolve to a host that satisfies different system constraints like current CPU load, physical Memory, Swap Memory, and time of day. This paper discusses the design and development of new scheme for ebXML registries that facilitates periodic collection and management of dynamic system properties for registry clients and enforces constraints during service discovery and query operation.
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A Load Balancing Scheme for ebXML Registries
2010 39th International Conference on Parallel Processing Workshops, 2010Co-Authors: Sadhana Sahasrabudhe, Christopher PaoliniAbstract:Large scale Service Oriented Architecture (SOA) developments are becoming increasingly reliant on registry services that manage Web Services using taxonomic attributes. At present a registry stores a Web Services interface definition and protocol bindings in WSDL, along with one or more XML schema files that define the structure of a SOAP message exchanged between Web Services operations and client processes and other static metadata. During Web Service discovery an ebXML registry returns the access URI associated with the service binding to allow dynamic discovery and invocation. This usually restricts a calling process to a Web Service invocation on one host. This work explores a mechanism to manage service bindings for a Web Service that has been deployed across multiple hosts, such that, a URI returned by a registry can resolve to a host that satisfies different system constraints like current CPU load, physical Memory, Swap Memory, and time of day. This paper discusses the design and development of new scheme for ebXML registries that facilitates periodic collection and management of dynamic system properties for registry clients and enforces constraints during service discovery and query operation.
