The Experts below are selected from a list of 1119 Experts worldwide ranked by ideXlab platform
Turhan Karadeniz - One of the best experts on this subject based on the ideXlab platform.
-
hardware design and implementation of a network on chip based load balancing Switch Fabric
Reconfigurable Computing and FPGAs, 2012Co-Authors: Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, J J GarcialunaacevesAbstract:Network routers rely on an important hardware component, namely the Switch Fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A Switch Fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based Switch Fabric Architecture and: 1) propose an FPGA based hardware implementation of the NOC Switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our Architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other Architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.
-
hardware design and implementation of a network on chip based high performance crossbar Switch Fabric
2010Co-Authors: Turhan KaradenizAbstract:High-performance routers have the task of transmitting traffic in between the nodes of the Internet, the network of networks that carries the vast amount of information among billions of users. The Switch Fabric is the key building block of every router, and various Switch Fabric Architectures are used in the market products. The crossbar-based Switch Fabric Architectures (both buffered and unbuffered) offer very high performances and are widely used for high-performance routers. However their cost grows quadratically with the input/output port count, since they require internal crosspoints (and buffers) for every input/output port pair. Recently, a functional-level design of two novel Network-on-Chip based Switch Fabric Architectures was proposed, Unidirectional NoC (UDN) and Multidirectional NoC (MDN), as a replacement of the buffered crossbar Switch Fabric Architecture. In this thesis, we propose the hardware design and implementation of the aforementioned Architectures for the FPGA platform. We further improve the routing and scheduling algorithms of these Architectures for feasible hardware design. The synthesis and simulations are carried out over a wide range of Switch sizes and traffic scenarios. The simulation results are also validated on the FPGA platform, by generating pseudo-random destination addresses for the packets on LFSR based test modules. The results show that UDN outperforms MDN in terms of throughput, whereas MDN offers greater performance-cost ratio. Both Architectures offer scalability, flexibility and high performance, confirming the ideas in the original proposal.
J J Garcialunaaceves - One of the best experts on this subject based on the ideXlab platform.
-
hardware design and implementation of a network on chip based load balancing Switch Fabric
Reconfigurable Computing and FPGAs, 2012Co-Authors: Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, J J GarcialunaacevesAbstract:Network routers rely on an important hardware component, namely the Switch Fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A Switch Fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based Switch Fabric Architecture and: 1) propose an FPGA based hardware implementation of the NOC Switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our Architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other Architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.
Elizabeth Suet Hing Tse - One of the best experts on this subject based on the ideXlab platform.
-
Switch Fabric Architecture analysis for a scalable bi-directionally reconfigurable IP router
Journal of Systems Architecture, 2004Co-Authors: Elizabeth Suet Hing TseAbstract:This paper provides an in-depth analysis using six basic router functional requirements, a primary Switch Fabrics (SFs) selection criterion, and a semi-quantitative compliance scoring scheme for 10 SFs. The goal is to select candidates that can serve a hardware (HW)-wise scalable and bi-directionally reconfigurable Internet Protocol (IP) router. HW scalability and bi-directional HW reconfigurability for an IP router denote respectively its ability to (1) expand according to network traffic capacity growth; and (2) be functionally converted to perform in two conceptual directions on-demand: "downward" as "edge", or "upward" as "hub" or "backbone" router according to the layer of the internet services provider's network hierarchy it is targeted to serve at the moment. Overall result points to Hypercube, Multistage Interconnection Network (MIN), and 3-Dimensional Torus Mesh as potential candidates.
Lotfi Mhamdi - One of the best experts on this subject based on the ideXlab platform.
-
hardware design and implementation of a network on chip based load balancing Switch Fabric
Reconfigurable Computing and FPGAs, 2012Co-Authors: Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, J J GarcialunaacevesAbstract:Network routers rely on an important hardware component, namely the Switch Fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A Switch Fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based Switch Fabric Architecture and: 1) propose an FPGA based hardware implementation of the NOC Switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our Architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other Architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.
Kees Goossens - One of the best experts on this subject based on the ideXlab platform.
-
hardware design and implementation of a network on chip based load balancing Switch Fabric
Reconfigurable Computing and FPGAs, 2012Co-Authors: Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, J J GarcialunaacevesAbstract:Network routers rely on an important hardware component, namely the Switch Fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A Switch Fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding. In this paper, we revisit our previously proposed Network-on-Chip (NOC) based Switch Fabric Architecture and: 1) propose an FPGA based hardware implementation of the NOC Switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and 3) present results in terms of throughput, average latency, and average bitrate. Our results show that our Architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other Architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.
