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The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform

P Das - One of the best experts on this subject based on the ideXlab platform.

D. Rana - One of the best experts on this subject based on the ideXlab platform.

  • The ICAP parallel processor communications switch
    IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: D. Rana, Charles C. Weems
    Abstract:

    The architecture of a custom VLSI parallel communications switch (PARCOS) chip is described. The PARCOS chip consists of a communication matrix of 32-b serial inputs and 32-b serial outputs and an on-chip control memory. The control memory, called the Connection pattern cache (CPC), is constructed so that PARCOS can hold up to 32 of the most frequently used Connection patterns between its inputs and outputs. Any of these stored patterns is incrementally modifiable, and the Connection pattern of the communication matrix can be Switched from one stored pattern in the CPC to another, with a single instruction. This chip is used in building an easily reconfigurable, circuit-Switched Connection network for the interprocessor communication of the intermediate-level processors of the Image Understanding Architecture (IUA) prototype. >

  • An easily reconfigurable, circuit Switched Connection network
    1988. IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: D. Rana, Charles C. Weems, Steven P. Levitan
    Abstract:

    The design of an easily reconfigurable, centrally controlled circuit-Switched Connection network is described. It is used as the interConnection network of a highly parallel processor, which in turn forms the intermediate (IUA) prototype. For an N-input N-output system, all of the possible N/sup N/ mappings of the inputs onto the outputs can be realized. Several interConnection patterns can be stored in the control memory of the interConnection network at once, allowing the network controller to change the Connection pattern of the intermediate level processors with exactly one instruction. Any of the stored Connection patterns can be completely overwritten by the controller with a new pattern from external memory by a series of instructions. If, however, only a subset of a Connection pattern in the control memory needs to be changed, the controller can do so by directly changing just those Connections that need to be modified. A 64*64 network built using custom chips is described in detail and some options for building larger networks are discussed. >

Charles C. Weems - One of the best experts on this subject based on the ideXlab platform.

  • The ICAP parallel processor communications switch
    IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: D. Rana, Charles C. Weems
    Abstract:

    The architecture of a custom VLSI parallel communications switch (PARCOS) chip is described. The PARCOS chip consists of a communication matrix of 32-b serial inputs and 32-b serial outputs and an on-chip control memory. The control memory, called the Connection pattern cache (CPC), is constructed so that PARCOS can hold up to 32 of the most frequently used Connection patterns between its inputs and outputs. Any of these stored patterns is incrementally modifiable, and the Connection pattern of the communication matrix can be Switched from one stored pattern in the CPC to another, with a single instruction. This chip is used in building an easily reconfigurable, circuit-Switched Connection network for the interprocessor communication of the intermediate-level processors of the Image Understanding Architecture (IUA) prototype. >

  • An easily reconfigurable, circuit Switched Connection network
    1988. IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: D. Rana, Charles C. Weems, Steven P. Levitan
    Abstract:

    The design of an easily reconfigurable, centrally controlled circuit-Switched Connection network is described. It is used as the interConnection network of a highly parallel processor, which in turn forms the intermediate (IUA) prototype. For an N-input N-output system, all of the possible N/sup N/ mappings of the inputs onto the outputs can be realized. Several interConnection patterns can be stored in the control memory of the interConnection network at once, allowing the network controller to change the Connection pattern of the intermediate level processors with exactly one instruction. Any of the stored Connection patterns can be completely overwritten by the controller with a new pattern from external memory by a series of instructions. If, however, only a subset of a Connection pattern in the control memory needs to be changed, the controller can do so by directly changing just those Connections that need to be modified. A 64*64 network built using custom chips is described in detail and some options for building larger networks are discussed. >

Jamil Y Khan - One of the best experts on this subject based on the ideXlab platform.

Steven P. Levitan - One of the best experts on this subject based on the ideXlab platform.

  • An easily reconfigurable, circuit Switched Connection network
    1988. IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: D. Rana, Charles C. Weems, Steven P. Levitan
    Abstract:

    The design of an easily reconfigurable, centrally controlled circuit-Switched Connection network is described. It is used as the interConnection network of a highly parallel processor, which in turn forms the intermediate (IUA) prototype. For an N-input N-output system, all of the possible N/sup N/ mappings of the inputs onto the outputs can be realized. Several interConnection patterns can be stored in the control memory of the interConnection network at once, allowing the network controller to change the Connection pattern of the intermediate level processors with exactly one instruction. Any of the stored Connection patterns can be completely overwritten by the controller with a new pattern from external memory by a series of instructions. If, however, only a subset of a Connection pattern in the control memory needs to be changed, the controller can do so by directly changing just those Connections that need to be modified. A 64*64 network built using custom chips is described in detail and some options for building larger networks are discussed. >

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