The Experts below are selected from a list of 135 Experts worldwide ranked by ideXlab platform
Ram Krishnamurthy - One of the best experts on this subject based on the ideXlab platform.
-
220mv 900mv 794 584 754 gbps w reconfigurable gf 2 4 2 aes sms4 camellia Symmetric Key Cipher accelerator in 14nm tri gate cmos
Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Sanu K Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
-
VLSI Circuits - 220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 4 )2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Sanu Mathew, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
Reza Azarderakhsh - One of the best experts on this subject based on the ideXlab platform.
-
efficient fault diagnosis schemes for reliable lightweight cryptographic iso iec standard clefia benchmarked on asic and fpga
IEEE Transactions on Industrial Electronics, 2013Co-Authors: Mehran Mozaffarikermani, Reza AzarderakhshAbstract:Lightweight block Ciphers are essential for providing low-cost confidentiality to sensitive constrained applications. Nonetheless, this confidentiality does not guarantee their reliability in the presence of natural and malicious faults. In this paper, fault diagnosis schemes for the lightweight internationally standardized block Cipher CLEFIA are proposed. This Symmetric-Key Cipher is compatible with yet lighter in hardware than the Advanced Encryption Standard and enables the implementation of cryptographic functionality with low complexity and power consumption. To the best of the authors' knowledge, there has been no fault diagnosis scheme presented in the literature for the CLEFIA to date. In addition to providing fault diagnosis approaches for the linear blocks in the encryption and the decryption of the CLEFIA, error detection approaches are presented for the nonlinear S-boxes, applicable to their composite-field implementations as well as their lookup table realizations. Through fault-injection simulations, the proposed schemes are benchmarked, and it is shown that they achieve error coverage of close to 100%. Finally, both application-specific integrated circuit and field-programmable gate array implementations of the proposed error detection structures are presented to assess their efficiency and overhead. The proposed fault diagnosis architectures make the implementations of the International Organization for Standardization/International Electrotechnical Commission-standardized CLEFIA more reliable.
-
Efficient Fault Diagnosis Schemes for Reliable Lightweight Cryptographic ISO/IEC Standard CLEFIA Benchmarked on ASIC and FPGA
IEEE Transactions on Industrial Electronics, 2013Co-Authors: Mehran Mozaffari-kermani, Reza AzarderakhshAbstract:Lightweight block Ciphers are essential for providing low-cost confidentiality to sensitive constrained applications. Nonetheless, this confidentiality does not guarantee their reliability in the presence of natural and malicious faults. In this paper, fault diagnosis schemes for the lightweight internationally standardized block Cipher CLEFIA are proposed. This Symmetric-Key Cipher is compatible with yet lighter in hardware than the Advanced Encryption Standard and enables the implementation of cryptographic functionality with low complexity and power consumption. To the best of the authors' knowledge, there has been no fault diagnosis scheme presented in the literature for the CLEFIA to date. In addition to providing fault diagnosis approaches for the linear blocks in the encryption and the decryption of the CLEFIA, error detection approaches are presented for the nonlinear S-boxes, applicable to their composite-field implementations as well as their lookup table realizations. Through fault-injection simulations, the proposed schemes are benchmarked, and it is shown that they achieve error coverage of close to 100%. Finally, both application-specific integrated circuit and field-programmable gate array implementations of the proposed error detection structures are presented to assess their efficiency and overhead. The proposed fault diagnosis architectures make the implementations of the International Organization for Standardization/International Electrotechnical Commission-standardized CLEFIA more reliable.
Sudhir K Satpathy - One of the best experts on this subject based on the ideXlab platform.
-
220mv 900mv 794 584 754 gbps w reconfigurable gf 2 4 2 aes sms4 camellia Symmetric Key Cipher accelerator in 14nm tri gate cmos
Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Sanu K Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
-
VLSI Circuits - 220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 4 )2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Sanu Mathew, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
Steven K Hsu - One of the best experts on this subject based on the ideXlab platform.
-
220mv 900mv 794 584 754 gbps w reconfigurable gf 2 4 2 aes sms4 camellia Symmetric Key Cipher accelerator in 14nm tri gate cmos
Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Sanu K Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
-
VLSI Circuits - 220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 4 )2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Sanu Mathew, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
Amit Agarwal - One of the best experts on this subject based on the ideXlab platform.
-
220mv 900mv 794 584 754 gbps w reconfigurable gf 2 4 2 aes sms4 camellia Symmetric Key Cipher accelerator in 14nm tri gate cmos
Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Sanu K Mathew, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
-
VLSI Circuits - 220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 4 )2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Sudhir K Satpathy, Vikram B Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K Hsu, Sanu Mathew, Ram KrishnamurthyAbstract:A reconfigurable AES/SMS4/Camellia Symmetric-Key Cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(24)2 Sbox-based unified datapath with in-line Key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with Key-precompute, and shared round constant circuits result in a 9152 µm2design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV.
