The Experts below are selected from a list of 51435 Experts worldwide ranked by ideXlab platform
Juan Carlos Arceo - One of the best experts on this subject based on the ideXlab platform.
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the Design and verification of a high performance low control overhead aSynchronous differential equation solver
IEEE Transactions on Very Large Scale Integration Systems, 1998Co-Authors: Peter A. Beerel, Vida Vakilotojar, A E Dooply, Juan Carlos ArceoAbstract:This paper describes the Design and verification of a high-performance aSynchronous differential equation solver benchmark circuit. The Design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 3.3 V) to be 48% faster than any comparable Synchronous Design (Designed to operate at 100/spl deg/C and 3 V for the slow process corner). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
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the Design and verification of a high performance low control overhead aSynchronous differential equation solver
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997Co-Authors: Peter A. Beerel, Vida Vakilotojar, A E Dooply, Juan Carlos ArceoAbstract:This paper describes the Design and verification of a high-performance aSynchronous differential equation solver. The Design has low control overhead which allows the average-case delay to be 48% faster (tested at 22/spl deg/C and 3.3 V) than any comparable Synchronous Design (simulated at 100/spl deg/C and 3 V). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
Peter A. Beerel - One of the best experts on this subject based on the ideXlab platform.
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a Designer s guide to aSynchronous vlsi
2010Co-Authors: Peter A. Beerel, Recep O Ozdag, Marcos FerrettiAbstract:Bypass the limitations of Synchronous Design and create low power, higher performance circuits with shorter Design times using this practical guide to aSynchronous Design. The fundamentals of aSynchronous Design are covered, as is a large variety of Design styles, while the emphasis throughout is on practical techniques and real-world applications.
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the Design and verification of a high performance low control overhead aSynchronous differential equation solver
IEEE Transactions on Very Large Scale Integration Systems, 1998Co-Authors: Peter A. Beerel, Vida Vakilotojar, A E Dooply, Juan Carlos ArceoAbstract:This paper describes the Design and verification of a high-performance aSynchronous differential equation solver benchmark circuit. The Design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 3.3 V) to be 48% faster than any comparable Synchronous Design (Designed to operate at 100/spl deg/C and 3 V for the slow process corner). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
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the Design and verification of a high performance low control overhead aSynchronous differential equation solver
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997Co-Authors: Peter A. Beerel, Vida Vakilotojar, A E Dooply, Juan Carlos ArceoAbstract:This paper describes the Design and verification of a high-performance aSynchronous differential equation solver. The Design has low control overhead which allows the average-case delay to be 48% faster (tested at 22/spl deg/C and 3.3 V) than any comparable Synchronous Design (simulated at 100/spl deg/C and 3 V). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
D Lundqvist - One of the best experts on this subject based on the ideXlab platform.
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lowering power consumption in clock by using globally aSynchronous locally Synchronous Design style
Design Automation Conference, 1999Co-Authors: Ahmed Hemani, T Meincke, Adam Postula, T Olsson, P Nilsson, Johnny Oberg, Peeter Ellervee, S. Kumar, D LundqvistAbstract:Power consumption in clock of large high performance VLSIs can be reduced by adopting globally aSynchronous, locally Synchronous Design style (GALS). GALS has small overheads for the global aSynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of Synchronous blocks, and (b) automate the synthesis of the global aSynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads.
Ralf Wollowski - One of the best experts on this subject based on the ideXlab platform.
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optimising bundled data balsa circuits
IEEE International Symposium on Asynchronous Circuits and Systems, 2016Co-Authors: Norman Kluge, Ralf WollowskiAbstract:Balsa provides a Design flow where aSynchronous circuits are created from high-level specifications, but the syntaxdriven translation often results in performance overhead. To improve this, we exploit the fact that bundled-data circuits can be divided into data and control path. Hence, tailored optimisation techniques can be applied to both paths separately. For control path optimisation, STG-based resynthesis has been introduced (applying logic minimisation). However, solid results are missing so far due to problems with state explosion and the reliable insertion of reset logic. To tackle this, we use an adjusted STG decomposition algorithm and started to develop a new logic synthesizer (based on ideas of petrify) with proper reset insertion. Adding the adapted data path, we are now able to get first promising post synthesis simulation results using an industrial technology library (with a performance improvement of up to 23%). First experiments show additional potential for performance improvements (of up to 56%) when standard tools for Synchronous Design are applied to the data path.
Vida Vakilotojar - One of the best experts on this subject based on the ideXlab platform.
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the Design and verification of a high performance low control overhead aSynchronous differential equation solver
IEEE Transactions on Very Large Scale Integration Systems, 1998Co-Authors: Peter A. Beerel, Vida Vakilotojar, A E Dooply, Juan Carlos ArceoAbstract:This paper describes the Design and verification of a high-performance aSynchronous differential equation solver benchmark circuit. The Design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 3.3 V) to be 48% faster than any comparable Synchronous Design (Designed to operate at 100/spl deg/C and 3 V for the slow process corner). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
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the Design and verification of a high performance low control overhead aSynchronous differential equation solver
International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997Co-Authors: Peter A. Beerel, Vida Vakilotojar, A E Dooply, Juan Carlos ArceoAbstract:This paper describes the Design and verification of a high-performance aSynchronous differential equation solver. The Design has low control overhead which allows the average-case delay to be 48% faster (tested at 22/spl deg/C and 3.3 V) than any comparable Synchronous Design (simulated at 100/spl deg/C and 3 V). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.
