The Experts below are selected from a list of 171 Experts worldwide ranked by ideXlab platform
Joseph R Cavallaro - One of the best experts on this subject based on the ideXlab platform.
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multi layer parallel decoding algorithm and vlsi architecture for quasi cyclic ldpc codes
International Symposium on Circuits and Systems, 2011Co-Authors: Guohui Wang, Joseph R CavallaroAbstract:We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a Synthesis Area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
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ISCAS - Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Yang Sun, Guohui Wang, Joseph R CavallaroAbstract:We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a Synthesis Area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
Yang Sun - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Yang Sun, Guohui Wang, Joseph R CavallaroAbstract:We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a Synthesis Area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
Guohui Wang - One of the best experts on this subject based on the ideXlab platform.
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multi layer parallel decoding algorithm and vlsi architecture for quasi cyclic ldpc codes
International Symposium on Circuits and Systems, 2011Co-Authors: Guohui Wang, Joseph R CavallaroAbstract:We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a Synthesis Area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
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ISCAS - Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011Co-Authors: Yang Sun, Guohui Wang, Joseph R CavallaroAbstract:We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a Synthesis Area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
Ali Chamas Al Ghouwayel - One of the best experts on this subject based on the ideXlab platform.
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design of a gf 64 ldpc decoder based on the ems algorithm
IEEE Transactions on Circuits and Systems I-regular Papers, 2013Co-Authors: Emmanuel Boutillon, Laura Condecanencia, Ali Chamas Al GhouwayelAbstract:This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-Synthesis Area results show that the decoder Area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design.
Emmanuel Boutillon - One of the best experts on this subject based on the ideXlab platform.
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design of a gf 64 ldpc decoder based on the ems algorithm
IEEE Transactions on Circuits and Systems I-regular Papers, 2013Co-Authors: Emmanuel Boutillon, Laura Condecanencia, Ali Chamas Al GhouwayelAbstract:This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-Synthesis Area results show that the decoder Area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design.
