The Experts below are selected from a list of 182661 Experts worldwide ranked by ideXlab platform
Ritu Agarwal - One of the best experts on this subject based on the ideXlab platform.
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time flies when you re having fun cognitive absorption and beliefs about information Technology usage 1
Management Information Systems Quarterly, 2000Co-Authors: Ritu Agarwal, Elena KarahannaAbstract:Extant explanations of why users behave in particular ways toward information technologies have tended to focus predominantly on instrumental beliefs as drivers of individual usage intentions. Prior work in individual psychology, however, suggests that holistic experiences with Technology as captured in constructs such as enjoyment and flow are potentially important explanatory variables in Technology acceptance theories. In this paper, we describe a multi-dimensional construct labeled cognitive absorption and defined as a state of deep involvement with software. Cognitive absorption, theorized as being exhibited through the five dimensions of temporal dissociation, focused immersion, heightened enjoyment, control, and curiosity, is posited to be a proximal antecedent of two important beliefs about Technology use: perceived usefulness and perceived ease of use. In addition, we propose that the individual traits of playfulness and personal innovativeness are important determinants of cognitive absorption. Based on the conceptual definition of this construct, operational measures for each dimension are developed. Using the World Wide Web as the Target Technology, scale validation indicates that the operational measures have acceptable psychometric properties and confirmatory factor analysis supports the proposed multi-dimensional structure. Structural equation analysis provides evidence for the theorized nomological net of cognitive absorption. Theoretical and practical implications are offered
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the role of innovation characteristics and perceived voluntariness in the acceptance of information technologies
Decision Sciences, 1997Co-Authors: Ritu Agarwal, Jayesh PrasadAbstract:The often paradoxical relationship between investment in information Technology and gains in productivity has recently been attributed to a lack of user acceptance of information Technology innovations. Diverse streams of research have attempted to explain and predict user acceptance of new information technologies. A common theme underlying these various research streams is the inclusion of the perceived characteristics of an innovation as key independent variables. Furthermore, prior research has utilized different outcomes to represent user acceptance behavior. In this paper we focus on individual's perceptions about the characteristics of the Target Technology as explanatory and predictive variables for acceptance behavior, and present an empirical study examining the effects of these perceptions on two frequently used outcomes in the context of the innovation represented by the World Wide Web. The two outcomes examined are initial use of an innovation and intentions to continue such use in the future, that is, to routinize Technology use. Two research questions motivated and guided the study. First, are the perceptions that predict initial use the same as those that predict future use intentions? Our results confirm, as hypothesized by prior research, that innovation characteristics do explain acceptance behavior. The results further reveal that the specific characteristics that are relevant for each acceptance outcome are different. The second research question asks if perceived voluntariness plays a role in Technology acceptance. Results show that external pressure has an impact on adopters' acceptance behavior. Theoretical and practical implications that follow are presented.
Makoto Nagata - One of the best experts on this subject based on the ideXlab platform.
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A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
IEICE Transactions on Electronics, 2011Co-Authors: Takushi Hashida, Yuuki Araga, Makoto NagataAbstract:A diagnosis testbench of analog IP cores characterizes their coupling strengths against on-chip environmental disturbances, specifically with regard to substrate voltage variations. The testbench incorporates multi-tone digital noise generators and a precision waveform capture with multiple probing channels. A prototype test bench fabricated in a 90-nm CMOS Technology demonstrates the diagnosis of substrate coupling up to 400MHz with dynamic range of more than 60dB. The coefficients of noise propagation as well as noise coupling on a silicon substrate are quantitatively derived for analog IP cores processed in a Target Technology, and further linked with noise awared EDA tooling for the successful adoption of such IP cores in SoC integration.
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a diagnosis testbench of analog ip cores against on chip environmental disturbances
VLSI Test Symposium, 2011Co-Authors: Takushi Hashida, Yuuki Araga, Makoto NagataAbstract:Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise generation circuits. The coefficients of noise propagation and noise coupling are quantitatively derived for fabless IP cores processed in a Target Technology, that will be further linked with EDA tooling for the successful adoption of such IP cores in SoC integration.
M Chang - One of the best experts on this subject based on the ideXlab platform.
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designing a java microprocessor core using fpga Technology
Computing & Control Engineering Journal, 2000Co-Authors: A Kim, M ChangAbstract:Ever since its introduction from Sun Microsystems four years ago (1996), Java has been widely accepted in the computing and Internet industry. However, the runtime performance is still not good enough for Java to become a general-purpose programming language. The article shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the field programmable gate array is chosen as a Target Technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.
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designing a java microprocessor core using fpga Technology
International Conference on ASIC, 1998Co-Authors: A Kim, M ChangAbstract:Ever since its introduction from Sun Microsystems three years ago, Java has been widely accepted in the computing and Internet industry. However the run-time performance is still not good enough for Java to become a general purpose programming language. This paper shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the Field Programmable Gate Array (FPGA) is chosen as a Target Technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.
Kamal Rajeev - One of the best experts on this subject based on the ideXlab platform.
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Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems
Universitat Politècnica de Catalunya, 2017Co-Authors: Kamal RajeevAbstract:Networks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences the modern high speed communication infrastructure to improve on-chip communication challenges in the recent many core System-on-Chip (SoC) designs. Continuing shrinkage of feature dimensions of Nano-scale semiconductor devices has been raised serious concerns of the reliability, signal integrity, and quality of services (QoS) of traditional bus based on-chip interconnect infrastructure. NoC represents a major standard move to address these concerns by incorporating state-of-the-art of high-speed data network components (such as routers and switches) and packet-based routing protocols in novel on-chip network infrastructure. A NoC¿s aim is to provide a reliable on-chip communication platform to facilitate scalable gigascale SoC design. A multi-synchronous bi-directional NoC's router architecture is proposed in this thesis to enhance the performance of available on-chip communication platform. Using parameterized RTL implementation, we first divide microarchitecture into six blocks as multi-synchronous FIFO, Arbiters, Route Computation, Switch Allocator, Virtual channel Allocator, and Network Interface. Overall architecture of the proposed NoC router consists of five bi-directional ports which supports data transfer between two clock domain of completely arbitrary phase and frequency; and best suited for the Distributed Scalable Predictable Interconnect Networks (DSPIN). In this router, each communication channel allows itself to be dynamically reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. We first evaluated performances of each blocks in terms of power, area, and delay with optimizes these blocks to satisfy network key parameters, as well as the impact of allocation on overall network performance. Using structural modeling style and parametric Verilog HDL, all blocks are individually implemented, tested and verified. Finally, all individual blocks are combined to implement bi-directional router¿s architecture as a whole. Here, we vary the number of nodes for performance evaluation. A multi-synchronous bi-directional router microarchitecture have been implemented in this thesis, is sufficient to provide throughput challenges, interconnect issues, low latency and high bandwidth in the future Globally Asynchronous Locally Synchronous Systems (GALS) system. In concise, to enhance the performance of on-chip communications of GALS Systems, a dynamic reconfigurable multi-synchronous router architecture is proposed and implemented to increase the NoC efficiency with changing the path of the communication link in the runtime traffic situation. In order to address GALS issues and bandwidth requirements, the proposed multi-synchronous bidirectional NoC¿s router is developed and it gives reliable higher packet consumption rate, better bandwidth utilization with lower packet delivery latency. All the input/output ports of the proposed router behave as a bi-directional ports and communicate through a novel multi-synchronous first-in first-out (FIFO) buffer. The bidirectional port is controlled by a dynamic channel control module which provides a dynamic reconfigurable channel to the router itself and associated with sub-modules. This proposed multi-synchronous bidirectional router architecture is synthesized using Xilinx ISE 14.7 and FPGA Virtex 6 family device XC6VLX760 is considered as Target Technology. The performance of the proposed architecture is evaluated in terms of power, area, and delay.Las redes en chip (NoC) constituyen una plataforma de interconexión en chip emergente que influye en la moderna infraestructura de comunicación de alta velocidad para mejorar los desafíos de comunicación en chip de los recientes diseños de sistemas en chip (SoC). La continua reducción de las dimensiones de los dispositivos semiconductores a escala nanométrica ha planteado serias preocupaciones en cuanto a la fiabilidad, la integridad de la señal y la calidad de los servicios (QoS) de la infraestructura de interconexión en chip basada en canal tradicional. NoC representa un paso estándar importante para abordar estas cuestiones incorporando tecnología moderna de componentes de red de datos de alta velocidad (como enrutadores y conmutadores) y protocolos de enrutamiento basados en paquetes en la nueva infraestructura de red en chip. El objetivo de NoC es proporcionar una plataforma de comunicación en chip fiable para facilitar el diseño escalable de SoC. En esta tesis se propone una arquitectura de enrutador NoC bidireccional multi-síncrono para mejorar el rendimiento de la plataforma de comunicación en chip disponible. Utilizando una implementación RTL parametrizada, primero dividimos la microarquitectura en seis bloques como FIFO multi-síncrono, arbitradores, Cálculo de Rutas, Asignador de Conmutadores, Asignador de canales virtuales e Interfaz de Red. La arquitectura general del enrutador NoC propuesto consta de cinco puertos bidireccionales que soportan la transferencia de datos entre dos dominios de reloj de fase y frecuencia completamente arbitrarias; además, se muestra más adecuada para las Redes de Interconexión Predecibles Escalables y Distribuidas (DSPIN). En este enrutador, cada canal de comunicación permite ser reconfigurado dinámicamente para transmitir las unidades de control de flujo en cualquier dirección. Esta flexibilidad añadida promete una mejor utilización del ancho de banda, una menor latencia de entrega de paquetes y una mayor tasa de consumo de paquetes. Primero evaluamos las prestaciones de cada bloque en términos de potencia, área y retraso, optimizando estos bloques para satisfacer los parámetros clave de la red, así como el impacto de la asignación en el rendimiento general de la red. Utilizando el estilo de modelado estructural y el Verilog HDL paramétrico, todos los bloques se implementan, prueban y verifican individualmente. Finalmente, todos los bloques individuales se combinan para implementar la arquitectura de enrutador bidireccional como un todo. Aquí, variamos el número de nodos para la evaluación del rendimiento. En forma concisa, para mejorar el rendimiento de las comunicaciones en chip de los sistemas GALS, se propone e implementa una arquitectura de enrutador multi-síncrono reconfigurable dinámico para aumentar la eficiencia de NoC con el cambio de la ruta del enlace de comunicación en la situación de tráfico en tiempo de ejecución. Con el fin de abordar los problemas de GALS y los requisitos de la banda ancha, el enrutador de NoC bidireccional multi-síncrono propuesto se desarrolla y proporciona una mayor tasa de consumo de paquetes, una mejor utilización de la banda ancha con menor latencia de entrega de paquetes. Todos los puertos de entrada / salida del enrutador propuesto se comportan como puertos bidireccionales y se comunican a través de un nuevo búfer multi-síncrono de tipo FIFO (primera entrada primera salida). El puerto bidireccional es controlado por un módulo de control de canal dinámico que proporciona un canal reconfigurable dinámico al propio enrutador y asociado con sub-módulos. Esta propuesta arquitectura de enrutador bidireccional multi-síncrono se sintetiza utilizando Xilinx ISE 14.7 y el dispositivo FPGA Virtex 6 XC6VLX760 se considera como la tecnología objetivo. El rendimiento de la arquitectura propuesta se evalúa en términos de potencia, área y retraso.Postprint (published version
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Contribution to the architecture and implementation of Bi-NoC routers for multi-synchronous GALS systems
Universitat Politècnica de Catalunya, 2017Co-Authors: Kamal RajeevAbstract:Networks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences the modern high speed communication infrastructure to improve on-chip communication challenges in the recent many core System-on-Chip (SoC) designs. Continuing shrinkage of feature dimensions of Nano-scale semiconductor devices has been raised serious concerns of the reliability, signal integrity, and quality of services (QoS) of traditional bus based on-chip interconnect infrastructure. NoC represents a major standard move to address these concerns by incorporating state-of-the-art of high-speed data network components (such as routers and switches) and packet-based routing protocols in novel on-chip network infrastructure. A NoC¿s aim is to provide a reliable on-chip communication platform to facilitate scalable gigascale SoC design. A multi-synchronous bi-directional NoC's router architecture is proposed in this thesis to enhance the performance of available on-chip communication platform. Using parameterized RTL implementation, we first divide microarchitecture into six blocks as multi-synchronous FIFO, Arbiters, Route Computation, Switch Allocator, Virtual channel Allocator, and Network Interface. Overall architecture of the proposed NoC router consists of five bi-directional ports which supports data transfer between two clock domain of completely arbitrary phase and frequency; and best suited for the Distributed Scalable Predictable Interconnect Networks (DSPIN). In this router, each communication channel allows itself to be dynamically reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. We first evaluated performances of each blocks in terms of power, area, and delay with optimizes these blocks to satisfy network key parameters, as well as the impact of allocation on overall network performance. Using structural modeling style and parametric Verilog HDL, all blocks are individually implemented, tested and verified. Finally, all individual blocks are combined to implement bi-directional router¿s architecture as a whole. Here, we vary the number of nodes for performance evaluation. A multi-synchronous bi-directional router microarchitecture have been implemented in this thesis, is sufficient to provide throughput challenges, interconnect issues, low latency and high bandwidth in the future Globally Asynchronous Locally Synchronous Systems (GALS) system. In concise, to enhance the performance of on-chip communications of GALS Systems, a dynamic reconfigurable multi-synchronous router architecture is proposed and implemented to increase the NoC efficiency with changing the path of the communication link in the runtime traffic situation. In order to address GALS issues and bandwidth requirements, the proposed multi-synchronous bidirectional NoC¿s router is developed and it gives reliable higher packet consumption rate, better bandwidth utilization with lower packet delivery latency. All the input/output ports of the proposed router behave as a bi-directional ports and communicate through a novel multi-synchronous first-in first-out (FIFO) buffer. The bidirectional port is controlled by a dynamic channel control module which provides a dynamic reconfigurable channel to the router itself and associated with sub-modules. This proposed multi-synchronous bidirectional router architecture is synthesized using Xilinx ISE 14.7 and FPGA Virtex 6 family device XC6VLX760 is considered as Target Technology. The performance of the proposed architecture is evaluated in terms of power, area, and delay.Las redes en chip (NoC) constituyen una plataforma de interconexión en chip emergente que influye en la moderna infraestructura de comunicación de alta velocidad para mejorar los desafíos de comunicación en chip de los recientes diseños de sistemas en chip (SoC). La continua reducción de las dimensiones de los dispositivos semiconductores a escala nanométrica ha planteado serias preocupaciones en cuanto a la fiabilidad, la integridad de la señal y la calidad de los servicios (QoS) de la infraestructura de interconexión en chip basada en canal tradicional. NoC representa un paso estándar importante para abordar estas cuestiones incorporando tecnología moderna de componentes de red de datos de alta velocidad (como enrutadores y conmutadores) y protocolos de enrutamiento basados en paquetes en la nueva infraestructura de red en chip. El objetivo de NoC es proporcionar una plataforma de comunicación en chip fiable para facilitar el diseño escalable de SoC. En esta tesis se propone una arquitectura de enrutador NoC bidireccional multi-síncrono para mejorar el rendimiento de la plataforma de comunicación en chip disponible. Utilizando una implementación RTL parametrizada, primero dividimos la microarquitectura en seis bloques como FIFO multi-síncrono, arbitradores, Cálculo de Rutas, Asignador de Conmutadores, Asignador de canales virtuales e Interfaz de Red. La arquitectura general del enrutador NoC propuesto consta de cinco puertos bidireccionales que soportan la transferencia de datos entre dos dominios de reloj de fase y frecuencia completamente arbitrarias; además, se muestra más adecuada para las Redes de Interconexión Predecibles Escalables y Distribuidas (DSPIN). En este enrutador, cada canal de comunicación permite ser reconfigurado dinámicamente para transmitir las unidades de control de flujo en cualquier dirección. Esta flexibilidad añadida promete una mejor utilización del ancho de banda, una menor latencia de entrega de paquetes y una mayor tasa de consumo de paquetes. Primero evaluamos las prestaciones de cada bloque en términos de potencia, área y retraso, optimizando estos bloques para satisfacer los parámetros clave de la red, así como el impacto de la asignación en el rendimiento general de la red. Utilizando el estilo de modelado estructural y el Verilog HDL paramétrico, todos los bloques se implementan, prueban y verifican individualmente. Finalmente, todos los bloques individuales se combinan para implementar la arquitectura de enrutador bidireccional como un todo. Aquí, variamos el número de nodos para la evaluación del rendimiento. En forma concisa, para mejorar el rendimiento de las comunicaciones en chip de los sistemas GALS, se propone e implementa una arquitectura de enrutador multi-síncrono reconfigurable dinámico para aumentar la eficiencia de NoC con el cambio de la ruta del enlace de comunicación en la situación de tráfico en tiempo de ejecución. Con el fin de abordar los problemas de GALS y los requisitos de la banda ancha, el enrutador de NoC bidireccional multi-síncrono propuesto se desarrolla y proporciona una mayor tasa de consumo de paquetes, una mejor utilización de la banda ancha con menor latencia de entrega de paquetes. Todos los puertos de entrada / salida del enrutador propuesto se comportan como puertos bidireccionales y se comunican a través de un nuevo búfer multi-síncrono de tipo FIFO (primera entrada primera salida). El puerto bidireccional es controlado por un módulo de control de canal dinámico que proporciona un canal reconfigurable dinámico al propio enrutador y asociado con sub-módulos. Esta propuesta arquitectura de enrutador bidireccional multi-síncrono se sintetiza utilizando Xilinx ISE 14.7 y el dispositivo FPGA Virtex 6 XC6VLX760 se considera como la tecnología objetivo. El rendimiento de la arquitectura propuesta se evalúa en términos de potencia, área y retraso
Takushi Hashida - One of the best experts on this subject based on the ideXlab platform.
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A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength
IEICE Transactions on Electronics, 2011Co-Authors: Takushi Hashida, Yuuki Araga, Makoto NagataAbstract:A diagnosis testbench of analog IP cores characterizes their coupling strengths against on-chip environmental disturbances, specifically with regard to substrate voltage variations. The testbench incorporates multi-tone digital noise generators and a precision waveform capture with multiple probing channels. A prototype test bench fabricated in a 90-nm CMOS Technology demonstrates the diagnosis of substrate coupling up to 400MHz with dynamic range of more than 60dB. The coefficients of noise propagation as well as noise coupling on a silicon substrate are quantitatively derived for analog IP cores processed in a Target Technology, and further linked with noise awared EDA tooling for the successful adoption of such IP cores in SoC integration.
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a diagnosis testbench of analog ip cores against on chip environmental disturbances
VLSI Test Symposium, 2011Co-Authors: Takushi Hashida, Yuuki Araga, Makoto NagataAbstract:Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise generation circuits. The coefficients of noise propagation and noise coupling are quantitatively derived for fabless IP cores processed in a Target Technology, that will be further linked with EDA tooling for the successful adoption of such IP cores in SoC integration.
