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Yvan Labiche - One of the best experts on this subject based on the ideXlab platform.
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a measurement framework for object oriented software Testability
Information & Software Technology, 2005Co-Authors: Samar Mouchawrab, Lionel C Briand, Yvan LabicheAbstract:Testing is an expensive activity in the development process of any software system. Measuring and assessing the Testability of software would help in planning testing activities and allocating required resources. More importantly, measuring software Testability early in the development process, during analysis or design stages, can yield the highest payoff as design refactoring can be used to improve Testability before the implementation starts. This paper presents a generic and extensible measurement framework for object-oriented software Testability, which is based on a theory expressed as a set of operational hypotheses. We identify design attributes that have an impact on Testability directly or indirectly, by having an impact on testing activities and sub-activities. We also describe the cause-effect relationships between these attributes and software Testability based on thorough review of the literature and our own testing experience. Following the scientific method, we express them as operational hypotheses to be further tested. For each attribute, we provide a set of possible measures whose applicability largely depends on the level of details of the design documents and the testing techniques to be applied. The goal of this framework is twofold: (1) to provide structured guidance for practitioners trying to measure design Testability, (2) to provide a theoretical framework for facilitating empirical research on Testability.
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a uml based approach to system testing
Lecture Notes in Computer Science, 2001Co-Authors: Lionel C Briand, Yvan LabicheAbstract:System testing is concerned with testing an entire system based on its specifications. In the context of object-oriented, UML development, this means that system test requirements are derived from UML analysis artifacts such as use cases, their corresponding sequence and collaboration diagrams, class diagrams, and possibly the use of the Object Constraint Language across all these artifacts. Our goal is to support the derivation of test requirements, which will be transformed into test cases, test oracles, and test drivers once we have detailed design information.Another important issue we address is the one of Testability. Testability requirements (or rules) need to be imposed on UML artifacts so as to be able to support system testing efficiently. Those Testability requirements result from a trade-off between analysis and design overhead and improved Testability. The potential for automation is also an overriding concern all across our work as the ultimate goal is to fully support testing activities with high-capability tools.
A.n. Trahtman - One of the best experts on this subject based on the ideXlab platform.
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algorithms finding the order of local Testability of deterministic finite automaton and estimations of the order
Theoretical Computer Science, 2000Co-Authors: A.n. TrahtmanAbstract:Abstract A locally testable language L is a language with the property that for some nonnegative integer k , called the order or the level of local Testability, whether or not a word u is in the language L depends on (1) the prefix and suffix of the word u of length k−1 and (2) the set of intermediate substrings of length k of the word u . For given k the language is called k -testable. A finite deterministic automaton is called k -testable if the automaton accepts a k -testable language. In this paper, algorithms to verify 2-Testability of order O (n 3 ) , 3-Testability of order O (n 4 ) and j -Testability for j>3 of order O (n j+1 ) are presented. An O (n n+2 ) time algorithm of finding the precise order of local Testability is described. The time complexity of the algorithms improves on the previously known algorithms. We give necessary and sufficient conditions for an automaton to be k -testable in terms of the length of paths of related graphs. Some estimates of the upper and of the lower bound on the order of local Testability follow.
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precise estimation of the order of local Testability of a deterministic finite automaton
Lecture Notes in Computer Science, 1998Co-Authors: A.n. TrahtmanAbstract:A locally testable language L is a language with the property that for some nonnegative integer k, called the order or the level of local Testability, whether or not a word u in the language L depends on (1) the prefix and suffix of the word u of length k - 1 and (2) the set of intermediate substrings of length k of the word u. For given k the language is called k-testable. We give necessary and sufficient conditions for the language of an automaton to be k-testable in the terms of the length of paths of a related graph. Some estimations of the upper and of the lower bound of order of Testability follow from these results. We improve the upper bound on the order of Testability of locally testable deterministic finite automaton with n states to n 2 -n/2+1. This bound is the best possible. We give an answer on the following conjecture of Kim, McNaughton and McCloskey for deterministic finite locally testable automaton with n states: Is the order of local Testability no greater than Ω(n 1.5 ) when the alphabet size is two? Our answer is negative. In the case of size two the situation is the same as in general case: the order of local Testability is Ω(n 2 ).
S Manetti - One of the best experts on this subject based on the ideXlab platform.
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a symbolic program for parameter identifiability analysis in systems modeled via equivalent linear time invariant electrical circuits with application to electromagnetic harvesters
International Journal of Numerical Modelling-electronic Networks Devices and Fields, 2019Co-Authors: Giuseppe Fontana, S Manetti, Francesco Grasso, A Luchetta, M C Piccirilli, A ReattiAbstract:Accurate parameter identification is a patently crucial aspect of system modeling as far as analysis, design, control, maintenance, and fault diagnosis are concerned. In this respect, an essential prerequisite is to establish a priori the solvability degree of the parameter identification problem, which is accomplished by means of Testability analysis. The aim of this work is to present a program suitable for fully automated Testability analysis of any physical system that can be modeled by an equivalent analog linear time-invariant electrical circuit. Such a program has been obtained by combining the potentialities of symbolic techniques with the disclosures of a recently proposed theoretical approach to the Testability measure concept, able to circumvent the main shortcomings of early methods. An efficient program, characterized by better performances with respect to previous software packages, has been thereby developed, which is herein described from both an algorithmic and a functional viewpoint. It can be advantageously used by the workers interested in system modeling as a guide to devising or refining their own parameter identification strategies. Thoroughly discussed examples of application are also given, which include a complete Testability analysis and a novel parameter identification algorithm for electromagnetic harvesters.
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an unconditionally sound algorithm for Testability analysis in linear time invariant electrical networks
International Journal of Circuit Theory and Applications, 2016Co-Authors: Giuseppe Fontana, S Manetti, A Luchetta, M C PiccirilliAbstract:Summary The issue of Testability, intended as a measure of solvability of the parametric fault diagnosis problem in analog linear time-invariant electrical networks, is addressed in this paper. Independently of the considered fault location method, such important metric provides information as to how many and which components can be diagnosed. For the reader's convenience and to set up an appropriate framework for our main achievements, our first concern is to rederive fundamental results concerning analog linear time-invariant electrical network Testability hinging on multifrequency measurements. Then a novel algorithm for Testability analysis is proposed, which is straightforward and able to circumvent the main drawbacks of formerly proposed methods, such as computational and conceptual complexities, proneness to roundoff errors, and vulnerability to particular cases. A computer program that implements such algorithm is also described. Moreover, the possibility of employing further simplified versions of the latter and their links with a previously proposed approach are discussed on rigorous bases. Finally, examples are provided, which show the effectiveness and robustness of the new algorithms, also by means of a comparison with the old ones. Copyright © 2015 John Wiley & Sons, Ltd.
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finding ambiguity groups in low Testability analog circuits
IEEE Transactions on Circuits and Systems I-regular Papers, 2000Co-Authors: Janusz A Starzyk, J Pang, S Manetti, Maria Cristina Piccirilli, G FediAbstract:This paper discusses a numerically efficient approach to identify complex ambiguity groups for the purpose of analog fault diagnosis in low-Testability circuits. The approach presented uses a numerically efficient QR factorization technique applied to the Testability matrix. Various ambiguity groups are identified. This helps to find unique solution of fault diagnosis equations or identifies which groups of components can be uniquely determined. This work extends results reported earlier in literature, where QR factorization was used in low-Testability circuits, significantly increasing efficiency to determine ambiguity groups. A Matlab program that implements this method was integrated with a symbolic analysis program that generates test equations. The method is illustrated on two low-Testability electronic circuits. Finally, method efficiency is tested on larger electronic circuits with several hundred tested parameters.
Niraj K Jha - One of the best experts on this subject based on the ideXlab platform.
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tao regular expression based register transfer level Testability analysis and optimization
IEEE Transactions on Very Large Scale Integration Systems, 2001Co-Authors: S Ravi, Ganesh Lakshminarayana, Niraj K JhaAbstract:In this paper, we present Testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) Testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost Testability solution by examining the tradeoffs in choosing from a diverse array of Testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating Testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable.
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design for hierarchical Testability of rtl circuits obtained by behavioral synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997Co-Authors: Indradeep Ghosh, Anand Raghunathan, Niraj K JhaAbstract:In recent years, there has been growing interest in behavioral (high-level) synthesis for Testability. This is due to the fact that Testability features, such as scan or the built-in self-test, may incur large overheads if introduced during logic synthesis in the later phase of the design cycle. Related previous work attempted to generate system-level test sets using hierarchical Testability during behavioral synthesis. There, the test generation scheme is independent of bit width and is, therefore, capable of handling complex controller/data path circuits with large data path bit widths (e.g., 32), which has posed a serious challenge to logic-level sequential test generators. However, this previous work is not applicable when another high-level synthesis system is used. In this paper, we present techniques that add minimal test hardware to a given register-transfer level (RTL) circuit obtained by behavioral synthesis in order to ensure that the embedded elements in the circuit are hierarchically testable. An important byproduct of our design for Testability (DFT) procedure is a system-level test set that delivers precomputed test sets to each element in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the combined controller/data path. We performed extensive experiments with several complex controller/data path circuits synthesized by three different high-level synthesis systems which do not target Testability. The key advantages of our method, illustrated by these experiments, include: 1) the area, delay, and power overheads incurred for Testability are very low (the average area, delay, and power overheads for a large number of benchmarks are 3.5, 0.5, and 3.4%, respectively), 2) both the DFT hardware addition and test generation algorithms are independent of the data path bit width.
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genesis a behavioral synthesis system for hierarchical Testability
European Design and Test Conference, 1994Co-Authors: Sandeep Bhatia, Niraj K JhaAbstract:Previous research in the area of behavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance. We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical Testability. A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault effects from module outputs to system outputs. Genesis provided 100% system-level Testability for all the synthesized benchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an efficient gate-level sequential test generator. The area overhead of circuits synthesized by Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard Testability. Genesis can also easily handle loop constructs in the behavioral specification. >
Lionel C Briand - One of the best experts on this subject based on the ideXlab platform.
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a measurement framework for object oriented software Testability
Information & Software Technology, 2005Co-Authors: Samar Mouchawrab, Lionel C Briand, Yvan LabicheAbstract:Testing is an expensive activity in the development process of any software system. Measuring and assessing the Testability of software would help in planning testing activities and allocating required resources. More importantly, measuring software Testability early in the development process, during analysis or design stages, can yield the highest payoff as design refactoring can be used to improve Testability before the implementation starts. This paper presents a generic and extensible measurement framework for object-oriented software Testability, which is based on a theory expressed as a set of operational hypotheses. We identify design attributes that have an impact on Testability directly or indirectly, by having an impact on testing activities and sub-activities. We also describe the cause-effect relationships between these attributes and software Testability based on thorough review of the literature and our own testing experience. Following the scientific method, we express them as operational hypotheses to be further tested. For each attribute, we provide a set of possible measures whose applicability largely depends on the level of details of the design documents and the testing techniques to be applied. The goal of this framework is twofold: (1) to provide structured guidance for practitioners trying to measure design Testability, (2) to provide a theoretical framework for facilitating empirical research on Testability.
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a uml based approach to system testing
Lecture Notes in Computer Science, 2001Co-Authors: Lionel C Briand, Yvan LabicheAbstract:System testing is concerned with testing an entire system based on its specifications. In the context of object-oriented, UML development, this means that system test requirements are derived from UML analysis artifacts such as use cases, their corresponding sequence and collaboration diagrams, class diagrams, and possibly the use of the Object Constraint Language across all these artifacts. Our goal is to support the derivation of test requirements, which will be transformed into test cases, test oracles, and test drivers once we have detailed design information.Another important issue we address is the one of Testability. Testability requirements (or rules) need to be imposed on UML artifacts so as to be able to support system testing efficiently. Those Testability requirements result from a trade-off between analysis and design overhead and improved Testability. The potential for automation is also an overriding concern all across our work as the ultimate goal is to fully support testing activities with high-capability tools.
