The Experts below are selected from a list of 228 Experts worldwide ranked by ideXlab platform
Oliver Bringmann - One of the best experts on this subject based on the ideXlab platform.
-
simultime context sensitive Timing Simulation on intermediate code representation for rapid platform explorations
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast Timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive Simulations provide attractive benefits for Timing analysis. Nevertheless, these Simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive Timing Simulation based on the software intermediate representation. The assured Simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate Timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average Simulation throughput by 90% when at least four configurations are analyzed in parallel.
-
context sensitive Timing automata for fast source level Simulation
Design Automation and Test in Europe, 2017Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Christoph Gerum, Oliver BringmannAbstract:We present a novel technique for efficient source level Timing Simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in Simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level Simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level Timing Simulation. However, a direct application of the binary level approach to source level Simulation reduces Simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based Simulation technique. The proposed context-sensitive Timing automata enable an efficient evaluation of complex Simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache Simulation. The accelerated Simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation.
-
Accelerating source-level Timing Simulation
2016 Design Automation & Test in Europe Conference & Exhibition (DATE), 2016Co-Authors: Simon Schulz, Oliver BringmannAbstract:Source-level Timing Simulation (SLTS) is a promising method to overcome one major challenge in early and rapid prototyping: fast and accurate Simulation of Timing behavior. However, most of existing SLTS approaches are still coupled with a considerable Simulation overhead. We present a method to reduce source-level Timing Simulation overhead by removing superfluous instrumentation based on instrumentation dependency graphs. We show in experiments, that our optimizations decrease Simulation overhead significantly (up to factor 7.7), without losing accuracy. Our detailed experiments are based on benchmarks as well as real life production code, that is simulated in a virtual environment.
-
trace based context sensitive Timing Simulation considering execution path variations
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Jan Micha Borrmann, Sadik Asbach, Oliver BringmannAbstract:We present a fast and accurate Timing Simulation of binary code execution on complex embedded processors. Underlying block Timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on Timings observed in one hardware execution, Timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor.
-
context sensitive Timing Simulation of binary embedded software
Compilers Architecture and Synthesis for Embedded Systems, 2014Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Stefan Stattelmann, Oliver BringmannAbstract:We present an approach to accurately simulate the temporal behavior of binary embedded software based on Timing data generated using static analysis. As the Timing of an instruction sequence is significantly influenced by the mi-croarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during Simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive Simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary Simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the Simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional Simulation.
Wolfgang Rosenstiel - One of the best experts on this subject based on the ideXlab platform.
-
simultime context sensitive Timing Simulation on intermediate code representation for rapid platform explorations
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast Timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive Simulations provide attractive benefits for Timing analysis. Nevertheless, these Simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive Timing Simulation based on the software intermediate representation. The assured Simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate Timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average Simulation throughput by 90% when at least four configurations are analyzed in parallel.
-
context sensitive Timing automata for fast source level Simulation
Design Automation and Test in Europe, 2017Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Christoph Gerum, Oliver BringmannAbstract:We present a novel technique for efficient source level Timing Simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in Simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level Simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level Timing Simulation. However, a direct application of the binary level approach to source level Simulation reduces Simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based Simulation technique. The proposed context-sensitive Timing automata enable an efficient evaluation of complex Simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache Simulation. The accelerated Simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation.
-
trace based context sensitive Timing Simulation considering execution path variations
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Jan Micha Borrmann, Sadik Asbach, Oliver BringmannAbstract:We present a fast and accurate Timing Simulation of binary code execution on complex embedded processors. Underlying block Timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on Timings observed in one hardware execution, Timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor.
-
context sensitive Timing Simulation of binary embedded software
Compilers Architecture and Synthesis for Embedded Systems, 2014Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Stefan Stattelmann, Oliver BringmannAbstract:We present an approach to accurately simulate the temporal behavior of binary embedded software based on Timing data generated using static analysis. As the Timing of an instruction sequence is significantly influenced by the mi-croarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during Simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive Simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary Simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the Simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional Simulation.
-
high performance Timing Simulation of embedded software
Design Automation Conference, 2008Co-Authors: Jurgen Schnerr, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:This paper presents an approach for cycle-accurate Simulation of embedded software by integration in an abstract SystemC model. Compared to existing Simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of Simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static processor models. After that, the determined Timing information is back-annotated into SystemC for fast Simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch prediction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the Simulation host with approximately 90% of the speed of the untimed software without any code instrumentation.
Alexander Viehl - One of the best experts on this subject based on the ideXlab platform.
-
simultime context sensitive Timing Simulation on intermediate code representation for rapid platform explorations
Asia and South Pacific Design Automation Conference, 2019Co-Authors: Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:Nowadays, product lines are common practice in the embedded systems domain as they allow for substantial reductions in development costs and the time-to-market by a consequent application of design paradigms such as variability and structured reuse management. In that context, accurate and fast Timing predictions are essential for an early evaluation of all relevant variants of a product line concerning target platform properties. Context-sensitive Simulations provide attractive benefits for Timing analysis. Nevertheless, these Simulations depend strongly on a single configuration pair of compiler and hardware platform. To cope with this limitation, we present SIMULTime, a new technique for context-sensitive Timing Simulation based on the software intermediate representation. The assured Simulation throughput significantly increases by simulating simultaneously different hardware hardware platforms and compiler configurations. Multiple accurate Timing predictions are produced by running the simulator only once. Our novel approach was applied on several applications showing that SIMULTime increases the average Simulation throughput by 90% when at least four configurations are analyzed in parallel.
-
context sensitive Timing automata for fast source level Simulation
Design Automation and Test in Europe, 2017Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Christoph Gerum, Oliver BringmannAbstract:We present a novel technique for efficient source level Timing Simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in Simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level Simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level Timing Simulation. However, a direct application of the binary level approach to source level Simulation reduces Simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based Simulation technique. The proposed context-sensitive Timing automata enable an efficient evaluation of complex Simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache Simulation. The accelerated Simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation.
-
trace based context sensitive Timing Simulation considering execution path variations
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Jan Micha Borrmann, Sadik Asbach, Oliver BringmannAbstract:We present a fast and accurate Timing Simulation of binary code execution on complex embedded processors. Underlying block Timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on Timings observed in one hardware execution, Timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor.
-
context sensitive Timing Simulation of binary embedded software
Compilers Architecture and Synthesis for Embedded Systems, 2014Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Stefan Stattelmann, Oliver BringmannAbstract:We present an approach to accurately simulate the temporal behavior of binary embedded software based on Timing data generated using static analysis. As the Timing of an instruction sequence is significantly influenced by the mi-croarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during Simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive Simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary Simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the Simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional Simulation.
-
high performance Timing Simulation of embedded software
Design Automation Conference, 2008Co-Authors: Jurgen Schnerr, Alexander Viehl, Oliver Bringmann, Wolfgang RosenstielAbstract:This paper presents an approach for cycle-accurate Simulation of embedded software by integration in an abstract SystemC model. Compared to existing Simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of Simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static processor models. After that, the determined Timing information is back-annotated into SystemC for fast Simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch prediction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the Simulation host with approximately 90% of the speed of the untimed software without any code instrumentation.
G Jones - One of the best experts on this subject based on the ideXlab platform.
-
correcting for interstellar scattering delay in high precision pulsar Timing Simulation results
arXiv: Instrumentation and Methods for Astrophysics, 2015Co-Authors: N Palliyaguru, Daniel R Stinebring, M A Mclaughlin, Paul Demorest, G JonesAbstract:Light travel time changes due to gravitational waves may be detected within the next decade through precision Timing of millisecond pulsars. Removal of frequency-dependent interstellar medium (ISM) delays due to dispersion and scattering is a key issue in the detection process. Current Timing algorithms routinely correct pulse times of arrival (TOAs) for time-variable delays due to cold plasma dispersion. However, none of the major pulsar Timing groups correct for delays due to scattering from multi-path propagation in the ISM. Scattering introduces a frequency-dependent phase change in the signal that results in pulse broadening and arrival time delays. Any method to correct the TOA for interstellar propagation effects must be based on multi-frequency measurements that can effectively separate dispersion and scattering delay terms from frequency-independent perturbations such as those due to a gravitational wave. Cyclic spectroscopy, first described in an astronomical context by Demorest (2011), is a potentially powerful tool to assist in this multi-frequency decomposition. As a step toward a more comprehensive ISM propagation delay correction, we demonstrate through a Simulation that we can accurately recover impulse response functions (IRFs), such as those that would be introduced by multi-path scattering, with a realistic signal-to-noise ratio. We demonstrate that Timing precision is improved when scatter-corrected TOAs are used, under the assumptions of a high signal-to-noise and highly scattered signal. We also show that the effect of pulse-to-pulse "jitter" is not a serious problem for IRF reconstruction, at least for jitter levels comparable to those observed in several bright pulsars.
-
correcting for interstellar scattering delay in high precision pulsar Timing Simulation results
The Astrophysical Journal, 2015Co-Authors: N Palliyaguru, Daniel R Stinebring, M A Mclaughlin, Paul Demorest, G JonesAbstract:Light travel time changes due to gravitational waves (GWs) may be detected within the next decade through precision Timing of millisecond pulsars. Removal of frequency-dependent interstellar medium (ISM) delays due to dispersion and scattering is a key issue in the detection process. Current Timing algorithms routinely correct pulse times of arrival (TOAs) for time-variable delays due to cold plasma dispersion. However, none of the major pulsar Timing groups correct for delays due to scattering from multi-path propagation in the ISM. Scattering introduces a frequency-dependent phase change in the signal that results in pulse broadening and arrival time delays. Any method to correct the TOA for interstellar propagation effects must be based on multi-frequency measurements that can effectively separate dispersion and scattering delay terms from frequency-independent perturbations such as those due to a GW. Cyclic spectroscopy, first described in an astronomical context by Demorest (2011), is a potentially powerful tool to assist in this multi-frequency decomposition. As a step toward a more comprehensive ISM propagation delay correction, we demonstrate through a Simulation that we can accurately recover impulse response functions (IRFs), such as those that would be introduced by multi-path scattering, with a realistic signal-to-noise ratio (S/N). We demonstrate that Timing precision is improved when scatter-corrected TOAs are used, under the assumptions of a high S/N and highly scattered signal. We also show that the effect of pulse-to-pulse "jitter" is not a serious problem for IRF reconstruction, at least for jitter levels comparable to those observed in several bright pulsars.
Sebastian Ottlik - One of the best experts on this subject based on the ideXlab platform.
-
context sensitive Timing automata for fast source level Simulation
Design Automation and Test in Europe, 2017Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Christoph Gerum, Oliver BringmannAbstract:We present a novel technique for efficient source level Timing Simulation of embedded software execution on a target platform. In contrast to existing approaches, the proposed technique can accurately approximate time without requiring a dynamic cache model. Thereby the dramatic reduction in Simulation performance inherent to dynamic cache modeling is avoided. Consequently, our approach enables an exploitation of the performance potential of source level Simulation for complex microarchitectures that include caches. Our approach is based on recent advances in context-sensitive binary level Timing Simulation. However, a direct application of the binary level approach to source level Simulation reduces Simulation performance similarly to dynamic cache modeling. To overcome this performance limitation, we contribute a novel pushdown automaton based Simulation technique. The proposed context-sensitive Timing automata enable an efficient evaluation of complex Simulation logic with little overhead. Experimental results show that the proposed technique provides a speed up of an order of magnitude compared to existing context selection techniques and simple source level cache models. Simulation performance is similar to a state of the art accelerated cache Simulation. The accelerated Simulation is only applicable in specific circumstances, whereas the proposed approach does not suffer this limitation.
-
trace based context sensitive Timing Simulation considering execution path variations
Asia and South Pacific Design Automation Conference, 2016Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Jan Micha Borrmann, Sadik Asbach, Oliver BringmannAbstract:We present a fast and accurate Timing Simulation of binary code execution on complex embedded processors. Underlying block Timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on Timings observed in one hardware execution, Timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor.
-
context sensitive Timing Simulation of binary embedded software
Compilers Architecture and Synthesis for Embedded Systems, 2014Co-Authors: Sebastian Ottlik, Alexander Viehl, Wolfgang Rosenstiel, Stefan Stattelmann, Oliver BringmannAbstract:We present an approach to accurately simulate the temporal behavior of binary embedded software based on Timing data generated using static analysis. As the Timing of an instruction sequence is significantly influenced by the mi-croarchitecture state prior to its execution, which highly depends on the preceding control flow, a sequence must be separately considered for different control flow paths instead of estimating the influence of basic blocks or single instructions in isolation. We handle the thereby arising issue of an excessive or even infinite number of different paths by considering different execution contexts instead of control flow paths. Related approaches using context-sensitive cycle counts during Simulation are limited to simulating the control flow that could be considered during analysis. We eliminate this limitation by selecting contexts dynamically, picking a suitable one when no predetermined choice is available, thereby enabling a context-sensitive Simulation of unmodified binary code of concurrent programs, including asynchronous events such as interrupts. In contrast to other approximate binary Simulation techniques, estimates are conservative, yet tight, making our approach reliable when evaluating performance goals. For a multi-threaded application the Simulation deviates only by 0.24% from hardware measurements while the average overhead is only 50% compared to a purely functional Simulation.
