The Experts below are selected from a list of 9897 Experts worldwide ranked by ideXlab platform

Sambasivan Narayan - One of the best experts on this subject based on the ideXlab platform.

  • first order incremental block based statistical Timing analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan, D K Beece, Jeffrey S Piaget, Natesan Venkateswaran, Jeffrey G Hemmett
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivity of all Timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical Timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode Timing violations

  • first order incremental block based statistical Timing analysis
    Design Automation Conference, 2004
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivities of all Timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

Chandramouli Visweswariah - One of the best experts on this subject based on the ideXlab platform.

  • first order incremental block based statistical Timing analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan, D K Beece, Jeffrey S Piaget, Natesan Venkateswaran, Jeffrey G Hemmett
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivity of all Timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical Timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode Timing violations

  • first order incremental block based statistical Timing analysis
    Design Automation Conference, 2004
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivities of all Timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

Kaushik Ravindran - One of the best experts on this subject based on the ideXlab platform.

  • first order incremental block based statistical Timing analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan, D K Beece, Jeffrey S Piaget, Natesan Venkateswaran, Jeffrey G Hemmett
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivity of all Timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical Timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode Timing violations

  • first order incremental block based statistical Timing analysis
    Design Automation Conference, 2004
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivities of all Timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

Kerim Kalafala - One of the best experts on this subject based on the ideXlab platform.

  • first order incremental block based statistical Timing analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan, D K Beece, Jeffrey S Piaget, Natesan Venkateswaran, Jeffrey G Hemmett
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivity of all Timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical Timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode Timing violations

  • first order incremental block based statistical Timing analysis
    Design Automation Conference, 2004
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivities of all Timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

S G Walker - One of the best experts on this subject based on the ideXlab platform.

  • first order incremental block based statistical Timing analysis
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan, D K Beece, Jeffrey S Piaget, Natesan Venkateswaran, Jeffrey G Hemmett
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivity of all Timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical Timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode Timing violations

  • first order incremental block based statistical Timing analysis
    Design Automation Conference, 2004
    Co-Authors: Chandramouli Visweswariah, Kaushik Ravindran, Kerim Kalafala, S G Walker, Sambasivan Narayan
    Abstract:

    Variability in digital integrated circuits makes Timing Verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical Timing algorithm is employed to propagate Timing quantities like arrival times and required arrival times through the Timing graph in this canonical form. At the end of the statistical Timing, the sensitivities of all Timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the Timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.