Underlying Hardware

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Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep spiking neural networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing studies on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this paper, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a deep spiking neural network capable of performing high-accuracy and low-latency classification tasks, where the neural computing unit is enabled by the stochastic switching behavior of a magnetic tunnel junction. The simulation studies indicate an energy improvement of $20 \times $ over a baseline CMOS design in 45-nm technology.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    arXiv: Emerging Technologies, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep Spiking Neural Networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing literature on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this work, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a Deep Spiking Neural Network capable of performing high accuracy and low latency classification tasks where the neural computing unit is enabled by the stochastic switching behavior of a Magnetic Tunnel Junction. Simulation studies indicate an energy improvement of $20\times$ over a baseline CMOS design in $45nm$ technology.

Abhronil Sengupta - One of the best experts on this subject based on the ideXlab platform.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep spiking neural networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing studies on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this paper, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a deep spiking neural network capable of performing high-accuracy and low-latency classification tasks, where the neural computing unit is enabled by the stochastic switching behavior of a magnetic tunnel junction. The simulation studies indicate an energy improvement of $20 \times $ over a baseline CMOS design in 45-nm technology.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    arXiv: Emerging Technologies, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep Spiking Neural Networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing literature on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this work, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a Deep Spiking Neural Network capable of performing high accuracy and low latency classification tasks where the neural computing unit is enabled by the stochastic switching behavior of a Magnetic Tunnel Junction. Simulation studies indicate an energy improvement of $20\times$ over a baseline CMOS design in $45nm$ technology.

Mani Srivastava - One of the best experts on this subject based on the ideXlab platform.

  • energy aware wireless microsensor networks
    IEEE Signal Processing Magazine, 2002
    Co-Authors: Vijay Raghunathan, Curt Schurgers, Sung Park, Mani Srivastava
    Abstract:

    This article describes architectural and algorithmic approaches that designers can use to enhance the energy awareness of wireless sensor networks. The article starts off with an analysis of the power consumption characteristics of typical sensor node architectures and identifies the various factors that affect system lifetime. We then present a suite of techniques that perform aggressive energy optimization while targeting all stages of sensor network design, from individual nodes to the entire network. Maximizing network lifetime requires the use of a well-structured design methodology, which enables energy-aware design and operation of all aspects of the sensor network, from the Underlying Hardware platform to the application software and network protocols. Adopting such a holistic approach ensures that energy awareness is incorporated not only into individual sensor nodes but also into groups of communicating nodes and the entire sensor network. By following an energy-aware design methodology based on techniques such as in this article, designers can enhance network lifetime by orders of magnitude.

Bing Han - One of the best experts on this subject based on the ideXlab platform.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep spiking neural networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing studies on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this paper, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a deep spiking neural network capable of performing high-accuracy and low-latency classification tasks, where the neural computing unit is enabled by the stochastic switching behavior of a magnetic tunnel junction. The simulation studies indicate an energy improvement of $20 \times $ over a baseline CMOS design in 45-nm technology.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    arXiv: Emerging Technologies, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep Spiking Neural Networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing literature on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this work, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a Deep Spiking Neural Network capable of performing high accuracy and low latency classification tasks where the neural computing unit is enabled by the stochastic switching behavior of a Magnetic Tunnel Junction. Simulation studies indicate an energy improvement of $20\times$ over a baseline CMOS design in $45nm$ technology.

Maryam Parsa - One of the best experts on this subject based on the ideXlab platform.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep spiking neural networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing studies on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this paper, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a deep spiking neural network capable of performing high-accuracy and low-latency classification tasks, where the neural computing unit is enabled by the stochastic switching behavior of a magnetic tunnel junction. The simulation studies indicate an energy improvement of $20 \times $ over a baseline CMOS design in 45-nm technology.

  • probabilistic deep spiking neural systems enabled by magnetic tunnel junction
    arXiv: Emerging Technologies, 2016
    Co-Authors: Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
    Abstract:

    Deep Spiking Neural Networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing literature on such computing models are developed with limited insights on the Underlying Hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this work, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a Deep Spiking Neural Network capable of performing high accuracy and low latency classification tasks where the neural computing unit is enabled by the stochastic switching behavior of a Magnetic Tunnel Junction. Simulation studies indicate an energy improvement of $20\times$ over a baseline CMOS design in $45nm$ technology.