The Experts below are selected from a list of 6 Experts worldwide ranked by ideXlab platform
Kevin M. Lynch - One of the best experts on this subject based on the ideXlab platform.
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Chapter 6 – Interrupts
Embedded Computing and Mechatronics with the PIC32, 2016Co-Authors: Kevin M. LynchAbstract:Certain events generate Interrupts, which ask the CPU to stop what it is doing, perform another task, and then return to its previous task. Interrupts play an important role in real-time control systems and embedded computing. This chapter describes the PIC32’s handling of Interrupts, which can be generated by the CPU, peripherals, or sensor inputs. Concepts such as Interrupt requests (IRQs), Interrupt Vectors, Interrupt priorities, Interrupt flags, and Interrupt service routines (ISRs) are covered. The shadow register set is introduced as a way to eliminate the time needed for “context save and restore” when entering and exiting an Interrupt. The chapter also details the steps to set up and enable an Interrupt and provides sample code that generates Interrupts on changing inputs or timer events. The chapter concludes by describing ways to safely share data between Interrupt service routines and mainline code without generating race conditions.
Quan Kong - One of the best experts on this subject based on the ideXlab platform.
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Interrupt Support on the -VEX processor
2011Co-Authors: Quan KongAbstract:In this thesis, we present a design of Interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This Interrupt system is designed and implemented in four mechanisms to match different application requirements in terms of the hardware consumption and performance issues (Interrupt latency). On the other hand, due to the fact that the VEX compiler is not an open-source compiler, extra requirements to the assembler are also considered to make our work feasible. Our Interrupt system itself can also be parameterized to fit different applications. These parameters include the number of Interrupt Vectors, Interrupt priority of each vector and Interrupt Service Routines (ISRs) location address in the instruction memory. The testing results show that each version of our Interrupt system takes reasonable amount of hardware usage. We implemented our Interrupt system on a virtex-6 FPGA. Besides, the Interrupt latency can be reduced to only 2 clock cycles which is even better than some RISC-based softcore processors like Microblaze. This project creates a prototype of Interrupt system that could work on VLIW softcore processor which extends the functionality and capability of the processor such as running operating systems and establishing a multi-core system.
