The Experts below are selected from a list of 51534 Experts worldwide ranked by ideXlab platform
R G Sargent - One of the best experts on this subject based on the ideXlab platform.
-
Winter Simulation Conference - An introductory tutorial on Verification and Validation of simulation models
2015 Winter Simulation Conference (WSC), 2015Co-Authors: R G SargentAbstract:Model Verification and Validation are defined, and why model Verification and Validation are important is discussed. A graphical paradigm that shows how Verification and Validation are related to the model development process and a flowchart that shows how Verification and Validation is part of the model development process are presented and discussed. The three approaches to deciding model validity are described. Comments are made on the importance of model accuracy and documentation. An overview of conducting Verification and Validation is presented and a recommended procedure for Verification and Validation is given.
-
Verification and Validation of simulation models
Journal of Simulation, 2013Co-Authors: R G SargentAbstract:Verification and Validation of simulation models are discussed in this paper. Three approaches to deciding model validity are described, two paradigms that relate Verification and Validation to the model development process are presented, and various Validation techniques are defined. Conceptual model validity, model Verification, operational validity, and data validity are discussed. A way to document results is given, and a recommended procedure for model Validation is presented.
-
Verification and Validation of simulation models
Journal of Simulation, 2013Co-Authors: R G SargentAbstract:Verification and Validation of simulation models are discussed in this paper. Three approaches to deciding model validity are described, two paradigms that relate Verification and Validation to the...
-
Winter Simulation Conference - An introduction to Verification and Validation of simulation models
2013 Winter Simulations Conference (WSC), 2013Co-Authors: R G SargentAbstract:Model Verification and Validation are defined, and why model Verification and Validation are important is discussed. The three approaches to deciding model validity are described. A graphical paradigm that shows how Verification and Validation are related to the model development process and a flowchart that shows how Verification and Validation is part of the model development process are presented and discussed. A recommended procedure for Verification and Validation is given.
-
Winter Simulation Conference - Verification and Validation of simulation models
2008 Winter Simulation Conference, 2008Co-Authors: R G SargentAbstract:In this paper we discuss Verification and Validation of simulation models. Four different approaches to deciding model validity are described; two different paradigms that relate Verification and Validation to the model development process are presented; various Validation techniques are defined; conceptual model validity, model Verification, operational validity, and data validity are discussed; a way to document results is given; a recommended procedure for model Validation is presented; and model accreditation is briefly discussed.
Daniel E. O'leary - One of the best experts on this subject based on the ideXlab platform.
-
Toward a theory of Verification and Validation: Artifacts
International Journal of Intelligent Systems, 1994Co-Authors: Daniel E. O'learyAbstract:This article uses the notion of artifacts to generate a theory for the Verification and Validation of intelligent systems. This theory has a number of applications. First, it provides a language and a way of thinking about Verification and Validation. Second, it suggests that we examine not the processes used in the design and development of systems, but instead the tangible artifacts generated by those processes. Third, it broadens the base of the set of artifacts encompassed by the typical Verification and Validation processes to include more than just specifications and prototypes. Fourth, the use of artifacts leads to a redefinition of Verification and Validation in terms of artifacts. Fifth, Verification and Validation tests are tied to artifacts, so that the choice of a set of artifacts can be used as a means of generating a portfolio of tests to investigate each artifact and the interaction of artifacts. Sixth, relationships between artifacts can be defined as “operators” which can be isolated and investigated for their individual quality. Seventh, standards can be generated for specific artifacts and operators rather than for entire development processes. © 1994 John Wiley & Sons, Inc.
-
Expert system Verification and Validation: a survey and tutorial
Artificial Intelligence Review, 1993Co-Authors: Robert M. O'keefe, Daniel E. O'learyAbstract:Assuring the quality of an expert system is critical. A poor quality system may make costly errors resulting in considerable damage to the user or owner of the system, such as financial loss or human suffering. Hence Verification and Validation, methods and techniques aimed at ensuring quality, are fundamentally important. This paper surveys the issues, methods and techniques for verifying and vali- dating expert systems. Approaches to defining the quality of a system are discussed, drawing upon work in both computing and the model building disciplines, which leads to definitions of Verification and Validation and the associated concepts of credibility, assessment and evaluation. An approach to Verification based upon the detection of anomalies is presented, and related to the concepts of consistency, completeness, correctness and redundancy. Automated tools for expert system Verification are reviewed. Considerable attention is then given to the issues in structuring the Validation process, particularly the establishment of the criteria by which the system is judged, the need to maintain objectivity, and the concept of reliability. This is followed by a review of Validation methods for validating both the components of a system and the system as a whole, and includes examples of some useful statistical methods. Management of the Verification and Validation process is then considered, and it is seen that the location of methods for Verification and Validation in the development life-cycle is of prime importance.
-
Verification and Validation of case-based systems
Expert Systems with Applications, 1993Co-Authors: Daniel E. O'learyAbstract:Abstract Verification and Validation of artificially intelligent systems has been the focus of substantial recent research. However, little attention has been given in the literature to Verification and Validation for cased-based systems. The unique structure of cased-based systems is used to raised new Validation issues, develop new approaches to generating comparative solutions for Validation purposes, and investigate new approaches for examining the quality of the case base. In addition, this article presents new statistical and structural approaches designed to exploit unique aspects of case-based reasoning for Verification purposes.
Tingmao Chang - One of the best experts on this subject based on the ideXlab platform.
-
soc hw sw Verification and Validation
Asia and South Pacific Design Automation Conference, 2011Co-Authors: Chungyang Huang, Yufan Yin, Chihjen Hsu, Thomas B Huang, Tingmao ChangAbstract:In modern SoC design flow, Verification and Validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in Verification and Validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW Verification and Validation flow.
-
ASP-DAC - SoC HW/SW Verification and Validation
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011Co-Authors: Chungyang Huang, Yufan Yin, Chihjen Hsu, Thomas B Huang, Tingmao ChangAbstract:In modern SoC design flow, Verification and Validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in Verification and Validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW Verification and Validation flow.
Chungyang Huang - One of the best experts on this subject based on the ideXlab platform.
-
soc hw sw Verification and Validation
Asia and South Pacific Design Automation Conference, 2011Co-Authors: Chungyang Huang, Yufan Yin, Chihjen Hsu, Thomas B Huang, Tingmao ChangAbstract:In modern SoC design flow, Verification and Validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in Verification and Validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW Verification and Validation flow.
-
ASP-DAC - SoC HW/SW Verification and Validation
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011Co-Authors: Chungyang Huang, Yufan Yin, Chihjen Hsu, Thomas B Huang, Tingmao ChangAbstract:In modern SoC design flow, Verification and Validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in Verification and Validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW Verification and Validation flow.
Thomas B Huang - One of the best experts on this subject based on the ideXlab platform.
-
soc hw sw Verification and Validation
Asia and South Pacific Design Automation Conference, 2011Co-Authors: Chungyang Huang, Yufan Yin, Chihjen Hsu, Thomas B Huang, Tingmao ChangAbstract:In modern SoC design flow, Verification and Validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in Verification and Validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW Verification and Validation flow.
-
ASP-DAC - SoC HW/SW Verification and Validation
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011Co-Authors: Chungyang Huang, Yufan Yin, Chihjen Hsu, Thomas B Huang, Tingmao ChangAbstract:In modern SoC design flow, Verification and Validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in Verification and Validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW Verification and Validation flow.
