The Experts below are selected from a list of 15483 Experts worldwide ranked by ideXlab platform
Robert Bosch - One of the best experts on this subject based on the ideXlab platform.
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Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
2008 Design Automation and Test in Europe, 2008Co-Authors: Katharina Weinberger, Slava Bulach, Robert BoschAbstract:According to statistics the Verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design Process. This means that the Verification Process must be well structured and organized in order to efficiently reach desired Verification goals. This paper describes the modelling of an exhaustive formal Verification Process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow Process. The purpose of this work is to formalize and quantify the Verification Process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a Verification Process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.
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DATE - Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
2008 Design Automation and Test in Europe, 2008Co-Authors: Katharina Weinberger, Slava Bulach, Robert BoschAbstract:According to statistics the Verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design Process. This means that the Verification Process must be well structured and organized in order to efficiently reach desired Verification goals. This paper describes the modelling of an exhaustive formal Verification Process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow Process. The purpose of this work is to formalize and quantify the Verification Process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a Verification Process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.
Michael A. Temple - One of the best experts on this subject based on the ideXlab platform.
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MILCOM - An RF-DNA Verification Process for ZigBee networks
MILCOM 2012 - 2012 IEEE Military Communications Conference, 2012Co-Authors: Clay K. Dubendorfer, Benjamin W. Ramsey, Michael A. TempleAbstract:Impersonation of authorized network devices is a serious concern in applications involving monitoring and control of battlefield operations and military installation infrastructure-ZigBee is among the ad hoc network alternatives used for such purposes. There are considerable security concerns given the availability of ZigBee “hacking” tools that have evolved from methods used for IEEE 802.11 Wi-Fi and IEEE 802.15.1 Bluetooth attacks. To mitigate the effectiveness of these bit-level attacks, RF waveform features within the lowest OSI physical (PHY) layer are used to augment bit-level security mechanisms within higher OSI layers. The evolution of RF ‘Distinct Native Attribute’ (RF-DNA) fingerprinting continues here with a goal toward improving defensive RF Intelligence (RFINT) measures and enhancing rogue device detection. Demonstrations here involve ZigBee burst collection and RF-DNA fingerprint generation using experimentally collected emissions from like-model CC2420 ZigBee devices operating at 2.4 GHz. RF-DNA fingerprints from 7 authorized devices are used for Multiple Discriminant Analysis (MDA) training and authorized device classification performance assessed, i.e. answering: “Is the device 1 of M authorized devices?” Additional devices are introduced as impersonating rogue devices attempting to gain unauthorized network access by presenting false bit-level credentials for one of the M authorized devices. Granting or rejecting rogue network access is addressed using a claimed identity Verification Process, i.e, answering: “Does the device's current RF-DNA match its claimed bit-level identity?” For authorized devices, arbitrary classification and Verification benchmarks of %C> 90% and %V > 90% are achieved at SNR«10.0 dB using a test statistic based on assumed Multivariate Gaussian (MVG) likelihood values. Overall, rogue device rejection capability is promising using the same Verification test statistic, with %V < 10% (90% or better rejection) achieved for 11 of 14 rogue trials. One case yielded near 85% rogue Verification (unauthorized access) and security cannot be a matter of chance-work continues to find a more robust test statistic and improve the proposed Process.
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An RF-DNA Verification Process for ZigBee networks
MILCOM 2012 - 2012 IEEE Military Communications Conference, 2012Co-Authors: Clay K. Dubendorfer, Benjamin W. Ramsey, Michael A. TempleAbstract:Impersonation of authorized network devices is a serious concern in applications involving monitoring and control of battlefield operations and military installation infrastructure-ZigBee is among the ad hoc network alternatives used for such purposes. There are considerable security concerns given the availability of ZigBee “hacking” tools that have evolved from methods used for IEEE 802.11 Wi-Fi and IEEE 802.15.1 Bluetooth attacks. To mitigate the effectiveness of these bit-level attacks, RF waveform features within the lowest OSI physical (PHY) layer are used to augment bit-level security mechanisms within higher OSI layers. The evolution of RF `Distinct Native Attribute' (RF-DNA) fingerprinting continues here with a goal toward improving defensive RF Intelligence (RFINT) measures and enhancing rogue device detection. Demonstrations here involve ZigBee burst collection and RF-DNA fingerprint generation using experimentally collected emissions from like-model CC2420 ZigBee devices operating at 2.4 GHz. RF-DNA fingerprints from 7 authorized devices are used for Multiple Discriminant Analysis (MDA) training and authorized device classification performance assessed, i.e. answering: “Is the device 1 of M authorized devices?” Additional devices are introduced as impersonating rogue devices attempting to gain unauthorized network access by presenting false bit-level credentials for one of the M authorized devices. Granting or rejecting rogue network access is addressed using a claimed identity Verification Process, i.e, answering: “Does the device's current RF-DNA match its claimed bit-level identity?” For authorized devices, arbitrary classification and Verification benchmarks of %C>; 90% and %V >; 90% are achieved at SNR≈10.0 dB using a test statistic based on assumed Multivariate Gaussian (MVG) likelihood values. Overall, rogue device rejection capability is promising using the same Verification test - tatistic, with %V <; 10% (90% or better rejection) achieved for 11 of 14 rogue trials. One case yielded near 85% rogue Verification (unauthorized access) and security cannot be a matter of chance-work continues to find a more robust test statistic and improve the proposed Process.
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An RF-DNA Verification Process for ZigBee networks
MILCOM 2012 - 2012 IEEE Military Communications Conference, 2012Co-Authors: Clay K. Dubendorfer, Benjamin W. Ramsey, Michael A. TempleAbstract:Impersonation of authorized network devices is a serious concern in applications involving monitoring and control of battlefield operations and military installation infrastructure-ZigBee is among the ad hoc network alternatives used for such purposes. There are considerable security concerns given the availability of ZigBee “hacking” tools that have evolved from methods used for IEEE 802.11 Wi-Fi and IEEE 802.15.1 Bluetooth attacks. To mitigate the effectiveness of these bit-level attacks, RF waveform features within the lowest OSI physical (PHY) layer are used to augment bit-level security mechanisms within higher OSI layers. The evolution of RF `Distinct Native Attribute' (RF-DNA) fingerprinting continues here with a goal toward improving defensive RF Intelligence (RFINT) measures and enhancing rogue device detection. Demonstrations here involve ZigBee burst collection and RF-DNA fingerprint generation using experimentally collected emissions from like-model CC2420 ZigBee devices operating at 2.4 GHz. RF-DNA fingerprints from 7 authorized devices are used for Multiple Discriminant Analysis (MDA) training and authorized device classification performance assessed, i.e. answering: “Is the device 1 of M authorized devices?” Additional devices are introduced as impersonating rogue devices attempting to gain unauthorized network access by presenting false bit-level credentials for one of the M authorized devices. Granting or rejecting rogue network access is addressed using a claimed identity Verification Process, i.e, answering: “Does the device's current RF-DNA match its claimed bit-level identity?” For authorized devices, arbitrary classification and Verification benchmarks of %C>; 90% and %V >; 90% are achieved at SNR≈10.0 dB using a test statistic based on assumed Multivariate Gaussian (MVG) likelihood values. Overall, rogue device rejection capability is promising using the same Verification test statistic, with %V
Katharina Weinberger - One of the best experts on this subject based on the ideXlab platform.
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Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
2008 Design Automation and Test in Europe, 2008Co-Authors: Katharina Weinberger, Slava Bulach, Robert BoschAbstract:According to statistics the Verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design Process. This means that the Verification Process must be well structured and organized in order to efficiently reach desired Verification goals. This paper describes the modelling of an exhaustive formal Verification Process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow Process. The purpose of this work is to formalize and quantify the Verification Process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a Verification Process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.
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DATE - Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
2008 Design Automation and Test in Europe, 2008Co-Authors: Katharina Weinberger, Slava Bulach, Robert BoschAbstract:According to statistics the Verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design Process. This means that the Verification Process must be well structured and organized in order to efficiently reach desired Verification goals. This paper describes the modelling of an exhaustive formal Verification Process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow Process. The purpose of this work is to formalize and quantify the Verification Process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a Verification Process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.
Harald Vogt - One of the best experts on this subject based on the ideXlab platform.
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byte code Verification for java smart card based on model checking
European Symposium on Research in Computer Security, 1998Co-Authors: Joachim Posegga, Harald VogtAbstract:The paper presents a novel approach to Java byte code Verification: The Verification Process is performed “offline” on a network server, instead of incorporating it in the client. Furthermore, the most critical part of the Verification Process is based upon a formal model and uses a model checker for checking the Verification conditions. The result of the Verification Process can be securely communicated to the runtime platform with cryptographic means.
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ESORICS - Byte Code Verification for Java Smart Card Based on Model Checking
Computer Security — ESORICS 98, 1998Co-Authors: Joachim Posegga, Harald VogtAbstract:The paper presents a novel approach to Java byte code Verification: The Verification Process is performed “offline” on a network server, instead of incorporating it in the client. Furthermore, the most critical part of the Verification Process is based upon a formal model and uses a model checker for checking the Verification conditions. The result of the Verification Process can be securely communicated to the runtime platform with cryptographic means.
Slava Bulach - One of the best experts on this subject based on the ideXlab platform.
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Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
2008 Design Automation and Test in Europe, 2008Co-Authors: Katharina Weinberger, Slava Bulach, Robert BoschAbstract:According to statistics the Verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design Process. This means that the Verification Process must be well structured and organized in order to efficiently reach desired Verification goals. This paper describes the modelling of an exhaustive formal Verification Process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow Process. The purpose of this work is to formalize and quantify the Verification Process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a Verification Process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.
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DATE - Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
2008 Design Automation and Test in Europe, 2008Co-Authors: Katharina Weinberger, Slava Bulach, Robert BoschAbstract:According to statistics the Verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design Process. This means that the Verification Process must be well structured and organized in order to efficiently reach desired Verification goals. This paper describes the modelling of an exhaustive formal Verification Process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow Process. The purpose of this work is to formalize and quantify the Verification Process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a Verification Process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.
