The Experts below are selected from a list of 1431 Experts worldwide ranked by ideXlab platform
Julung Fann - One of the best experts on this subject based on the ideXlab platform.
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performance driven optimization for Video Accelerator design Video coding
International Symposium on Circuits and Systems, 2005Co-Authors: Chunfu Shen, Chikuang Chen, Julung FannAbstract:This paper presents a bandwidth-reduction oriented optimization for Video encoding upon a platform-based architecture. We develop a bit-true C simulation model to estimate the system performance as well as to accelerate the HW design time and shorten the simulation/verification iteration. Its customized architecture can provide a solid evaluation before a real design is undertaken. The proposed Accelerator contains two major modules which are designed by optimizing in bandwidth cost and application usage. The first one is a motion engine which takes charge of motion detection and estimation. The other module is a block engine which is well scheduled in block-based data flow and supports multi-standard (JPEG, H.263 and MPEG-4 SP) encoding. A novel data alignment method in frame memory reduces the bus bandwidth to 30% of the original. We verify our design in a 120 MHz AMBA platform and prove the capability of 30 fps VGA size encoding.
Amyrul Azuan Mohd Bahar - One of the best experts on this subject based on the ideXlab platform.
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Hardware Design and Thermal Management of Video Accelerator Cards in IOT Applications
2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2020Co-Authors: Eng Kwong Lee, Chin Seng Soon, Soon Choy Wong, Amyrul Azuan Mohd BaharAbstract:This paper demonstrates the hardware design and thermal solution of Video Accelerator cards in the M.2 and mini PCI express (mPCIe) form factor. The Video Accelerator cards have Video processing units (VPU) which act as extra graphics engine in addition to the processor in a system. It is the first in industry that Video Accelerator card can be designed in such small form factor without compromising performance. As the Accelerator cards are small, the board design can be of high challenge to ensure essential components and layout routing are done correctly to comply with design rules. In addition, high power density on the Accelerator cards requires good thermal design and power management to ensure the temperature on the VPU does not exceed specification during intended operation. The performance improvement on a host system equipped with the Accelerator cards will also be shown to prove the business acumen.
Zhou Hui - One of the best experts on this subject based on the ideXlab platform.
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performance analysis of tms320dm320 Video Accelerator imx
Information Technology, 2007Co-Authors: Zhou HuiAbstract:The fast development of mobile multimedia and Video compression raises higher requirement for hardware platform.TMS320DM320 is the multimedia processor of Texas Instruments.With the new architecture of ARM+DSP+Hard Engine IMX,it widely supports prevalent Video and audio compression standards.The hard engine IMX is high performance Video Accelerator,which supports multiple decoding operations.This thesis presents brief introduction of TMS320DM320.Based on the analysis of H.264 decoder,it discusses the optimization of decoding algorithms on IMX,tests and evaluates the performance of IMX on H.264 time-consuming algorithms,such as inverse transformation,inverse quantification and luminance MC.According to the results,with IMX,decoding operations could reach over 9x rate exaltation.
Pengfei Guo - One of the best experts on this subject based on the ideXlab platform.
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the design of Video Accelerator bus wrapper
CCF National Conference on Compujter Engineering and Technology, 2013Co-Authors: Longmei Nan, Pengfei GuoAbstract:Novel wrapper implementation technique is used to improve the data communication for Video processing Accelerator. The wrapper provided the function of flow control, data buffers and protocol analysis. It can reduce Video data transfer time up to 50% compared with the conventional CPU based data transfer method. At the same time, the wrapper’s area is 9278 μm2 and the operation clock frequency is 1GHz implemented using 0.13μm CMOS technologies.
Chunfu Shen - One of the best experts on this subject based on the ideXlab platform.
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performance driven optimization for Video Accelerator design Video coding
International Symposium on Circuits and Systems, 2005Co-Authors: Chunfu Shen, Chikuang Chen, Julung FannAbstract:This paper presents a bandwidth-reduction oriented optimization for Video encoding upon a platform-based architecture. We develop a bit-true C simulation model to estimate the system performance as well as to accelerate the HW design time and shorten the simulation/verification iteration. Its customized architecture can provide a solid evaluation before a real design is undertaken. The proposed Accelerator contains two major modules which are designed by optimizing in bandwidth cost and application usage. The first one is a motion engine which takes charge of motion detection and estimation. The other module is a block engine which is well scheduled in block-based data flow and supports multi-standard (JPEG, H.263 and MPEG-4 SP) encoding. A novel data alignment method in frame memory reduces the bus bandwidth to 30% of the original. We verify our design in a 120 MHz AMBA platform and prove the capability of 30 fps VGA size encoding.
