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Wafer

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U Gosele - One of the best experts on this subject based on the ideXlab platform.

  • Wafer scale integration of gaas optoelectronic devices with standard si integrated circuits using a low temperature bonding procedure
    Applied Physics Letters, 2002
    Co-Authors: A Georgakilas, U Gosele, G Deligeorgis, E Aperathitis, D Cengher, Z Hatzopoulos, Marin Alexe, Viorel Dragoi, E D Kyriakisbitzaros, K Minoglou
    Abstract:

    A methodology for the heterogeneous integration of epitaxial GaAs Wafers with fully processed standard bipolar complementary metal-oxide-semiconductor Si Wafers is presented. The complete low-temperature Wafer bonding process flow, including procedures for the Si Wafer planarization and GaAs substrate removal, has been developed and evaluated. The implementation of an in-plane optical link, consisting of an edge-emitting laser diode, a waveguide and a photodiode, is demonstrated.

  • semiconductor Wafer bonding science and technology
    1998
    Co-Authors: Q Y Tong, U Gosele
    Abstract:

    Basics of Interactions Between Flat Surfaces. Influence of Particles, Surface Steps, and Cavities. Surface Preparation and Room-Temperature Wafer Bonding. Thermal Treatment of Bonded Wafer Pairs. Thinning Procedures. Electrical Properties of Bonding Interfaces. Stresses in Bonded Wafers. Bonding of Dissimilar Materials. Bonding of Structured Wafers. Mainstream Applications. Emerging and Future Applications. Index.

  • low temperature silicon direct bonding for application in micromechanics bonding energies for different combinations of oxides
    Sensors and Actuators A-physical, 1998
    Co-Authors: Gertrud Dr Krauter, Andreas Schumacher, U Gosele
    Abstract:

    Plain or structured hydrophillic silicon Wafers covered with native oxide or with thermally grown oxide layers have been directly bonded at room temperature; afterwards, the samples were annealed at 100°C to 400°C. There is a significant difference in the observed bonding energy depending on the Wafer pairing chosen. If one or both Wafers are covered with a native oxide layer, high bonding strengths are reached even at low temperatures. This can be explained by the different diffusion behaviour of water molecules through a thick thermal oxide layer on one hand, and through a thin native oxide layer on the other hand. Two different methods for the activation of the Wafer surfaces just prior to bonding are described.

  • self propagating room temperature silicon Wafer bonding in ultrahigh vacuum
    Applied Physics Letters, 1995
    Co-Authors: U Gosele, H Stenzel, T Martini, J Steinkirchner, D Conrad, K Scheerschmidt
    Abstract:

    Wafer bonding of commercial 4 in. silicon Wafers has been performed at room temperature under ultrahigh vacuum conditions. After local initiation of the bonding process the bonding area is self‐propagating just as in the case of Wafer bonding under atmospheric conditions. The room‐temperature bonded Wafers, without any additional heat treatment show a bonding strength typical for bulk material.

  • denuded zone formation in carbon implanted silicon and its application to device quality silicon on insulator preparation
    Applied Physics Letters, 1993
    Co-Authors: Q Y Tong, H M You, G Cha, U Gosele
    Abstract:

    For producing ultrathin (<0.1 μm) device quality silicon‐on‐insulator (SOI) films, commercially available 4‐in. diameter (100) SOI Wafers with single‐crystal layer thickness of 1.5±0.5 μm were carbon‐implanted (190 keV and 3×1016 cm−2) followed by bonding to oxidized Si Wafers. The buried oxide in the SOI Wafers was used as the first etch stop and the second etch was stopped at the implanted carbon peak. The formation of a carbon denuded zone allowed us to obtain ≤900±50 A SOI films free of carbon precipitation. Since precision polishing to thin one Wafer of a bonded pair down to ±0.5 μm in thickness variation is available in industry, it should be possible to start the described SOI process with a bulk Si Wafer, rather than an expensive SOI Wafer, and obtain similar results.

Emanuel M Sachs - One of the best experts on this subject based on the ideXlab platform.

  • crack detection in crystalline silicon solar cells using dark field imaging
    Energy Procedia, 2017
    Co-Authors: Sarah Wieghold, Ashley E Morishige, Luke T Meyer, Tonio Buonassisi, Emanuel M Sachs
    Abstract:

    Abstract The high capital expenditure (capex) necessary to manufacture crystalline silicon PV modules negatively affects the levelized cost of electricity (¢/kWh) and critically impacts the rate at which the PV industry can scale up. Wafer, cell, and module fabrication with thin free-standing silicon Wafers is one key to reduce capex. Thin Wafers reduce capex associated with silicon refining and Wafer fabrication, which together sum to 58% of the total capex of silicon module manufacturing. In addition, thin Wafers directly and significantly reduce variable costs. However, introducing 50 μm thin free-standing Wafers into today’s manufacturing lines result in cracking, creating a yield-based disincentive. Due to the brittle nature of silicon, Wafer breakage is the major concern due to the high stress that is induced during processes in manufacturing lines. In this paper, we describe an improved method for edge micro-crack detection that can help enable low-capex, thin free-standing Si Wafers. We present a method of detecting and measuring cracks along Wafer edges by using a dark-field IR scattering imaging technique which enables detection of edge cracks at the micron scale.

Sarah Wieghold - One of the best experts on this subject based on the ideXlab platform.

  • crack detection in crystalline silicon solar cells using dark field imaging
    Energy Procedia, 2017
    Co-Authors: Sarah Wieghold, Ashley E Morishige, Luke T Meyer, Tonio Buonassisi, Emanuel M Sachs
    Abstract:

    Abstract The high capital expenditure (capex) necessary to manufacture crystalline silicon PV modules negatively affects the levelized cost of electricity (¢/kWh) and critically impacts the rate at which the PV industry can scale up. Wafer, cell, and module fabrication with thin free-standing silicon Wafers is one key to reduce capex. Thin Wafers reduce capex associated with silicon refining and Wafer fabrication, which together sum to 58% of the total capex of silicon module manufacturing. In addition, thin Wafers directly and significantly reduce variable costs. However, introducing 50 μm thin free-standing Wafers into today’s manufacturing lines result in cracking, creating a yield-based disincentive. Due to the brittle nature of silicon, Wafer breakage is the major concern due to the high stress that is induced during processes in manufacturing lines. In this paper, we describe an improved method for edge micro-crack detection that can help enable low-capex, thin free-standing Si Wafers. We present a method of detecting and measuring cracks along Wafer edges by using a dark-field IR scattering imaging technique which enables detection of edge cracks at the micron scale.

K Scheerschmidt - One of the best experts on this subject based on the ideXlab platform.

  • self propagating room temperature silicon Wafer bonding in ultrahigh vacuum
    Applied Physics Letters, 1995
    Co-Authors: U Gosele, H Stenzel, T Martini, J Steinkirchner, D Conrad, K Scheerschmidt
    Abstract:

    Wafer bonding of commercial 4 in. silicon Wafers has been performed at room temperature under ultrahigh vacuum conditions. After local initiation of the bonding process the bonding area is self‐propagating just as in the case of Wafer bonding under atmospheric conditions. The room‐temperature bonded Wafers, without any additional heat treatment show a bonding strength typical for bulk material.

Tadatomo Suga - One of the best experts on this subject based on the ideXlab platform.

  • room temperature direct bonding of silicon and quartz glass Wafers
    Applied Physics Letters, 2017
    Co-Authors: Chenxi Wang, Yuan Wang, Yanhong Tian, Chunqing Wang, Tadatomo Suga
    Abstract:

    We demonstrate a facile bonding method for combining Si/Si, Si/quartz, and quartz/quartz Wafers at room temperature (∼25 °C) using a one-step O2/CF4/H2O plasma treatment. The bonding strengths were significantly improved by adding a small amount of CF4 into the oxygen plasma, such that reliable and tight bonding was obtained after storage in ambient air for 24 h, even without employing heat. Moreover, by introducing water vapor during O2/CF4 plasma treatment, uniform Wafer bonding was spontaneously achieved without applying an external force. The fluorinated surface asperities appear to be softened more easily by the interfacial water stress corrosion, enabling reliable bonding at room temperature. Additionally, adding an optimized amount of water vapor to the O2/CF4 plasma increases sufficiently the amount of hydroxyl groups without eliminating the CF4 effect. The additional water adsorbed on the surface may help to close the gap between the bonded Wafers, resulting in better bonding efficiency.