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3d Array

The Experts below are selected from a list of 2412 Experts worldwide ranked by ideXlab platform

Jinfeng Kang – 1st expert on this subject based on the ideXlab platform

  • 3d Vertical RRAM Array and Device Co-design with Physics-based Spice Model
    2019 IEEE 13th International Conference on ASIC (ASICON), 2019
    Co-Authors: Weiiie Xu, Peng Huang, Yudi Zhao, Jinfeng Kang

    Abstract:

    This paper demonstrates the co-design of three-dimension (3d) Vertical Resistive Random Access Memory (RRAM) and the RRAM device. It presents a design consideration of 3d Vertical RRAM Array in terms of Array performance from the device point of view. A physics-based RRAM Spice model is used to evaluate the performance of 3d RRAM Array, including write access voltage, read margin, energy consumption and switching speed. The effects of device parameters, device parasitic capacitance, device variation and the 3d Array size are discussed for design consideration. The simulation results show that with carefully choosing the RRAM device material and structure, a fast-switching, low energy consumption 3d RRAM Array can be realized.

  • Towards high-speed, write-disturb tolerant 3d vertical RRAM Arrays
    2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014
    Co-Authors: Hong-yu Chen, Zizhen Jiang, Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bing Chen, Feifei Zhang, Liang Zhao, Shimeng Yu

    Abstract:

    3d RRAM Array suffers more serious reliability issues than 2D Array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3d vertical RRAM Array. Using a combination of experiments and simulations, a methodology is developed to enable Array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3d Array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

  • Design guidelines for 3d RRAM cross-point architecture
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Shimeng Yu, Hong-yu Chen, Yexin Deng, Zizhen Jiang, Jinfeng Kang, Peng Huang, Bing Chen, H.-s. Philip Wong

    Abstract:

    Design guidelines were proposed to evaluate and optimize the 3d RRAM cross-point architecture by a full-size 3d circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3d cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3d Array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.

Shimeng Yu – 2nd expert on this subject based on the ideXlab platform

  • Towards high-speed, write-disturb tolerant 3d vertical RRAM Arrays
    2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014
    Co-Authors: Hong-yu Chen, Zizhen Jiang, Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bing Chen, Feifei Zhang, Liang Zhao, Shimeng Yu

    Abstract:

    3d RRAM Array suffers more serious reliability issues than 2D Array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3d vertical RRAM Array. Using a combination of experiments and simulations, a methodology is developed to enable Array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3d Array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

  • Design guidelines for 3d RRAM cross-point architecture
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Shimeng Yu, Hong-yu Chen, Yexin Deng, Zizhen Jiang, Jinfeng Kang, Peng Huang, Bing Chen, H.-s. Philip Wong

    Abstract:

    Design guidelines were proposed to evaluate and optimize the 3d RRAM cross-point architecture by a full-size 3d circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3d cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3d Array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.

  • 3d vertical RRAM – Scaling limit analysis and demonstration of 3d Array operation
    2013 Symposium on VLSI Technology, 2013
    Co-Authors: Shimeng Yu, Hong-yu Chen, Yexin Deng, Zizhen Jiang, Jinfeng Kang, H.-s. Philip Wong

    Abstract:

    3d vertical RRAM scaling limit is investigated. 3d RRAM functionality along with a viable write/read scheme for the 3d Array are experimentally demonstrated for the first time, using plane electrode with thickness ™ down to 5 nm to minimize 3d stack height. Through 3d circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D Array can scale further to F=13 nm, 3d Array device density is 11× higher than a 2D Array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3d Array. To enlarge 3d Array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.

H.-s. Philip Wong – 3rd expert on this subject based on the ideXlab platform

  • Design guidelines for 3d RRAM cross-point architecture
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Shimeng Yu, Hong-yu Chen, Yexin Deng, Zizhen Jiang, Jinfeng Kang, Peng Huang, Bing Chen, H.-s. Philip Wong

    Abstract:

    Design guidelines were proposed to evaluate and optimize the 3d RRAM cross-point architecture by a full-size 3d circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3d cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3d Array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.

  • 3d vertical RRAM – Scaling limit analysis and demonstration of 3d Array operation
    2013 Symposium on VLSI Technology, 2013
    Co-Authors: Shimeng Yu, Hong-yu Chen, Yexin Deng, Zizhen Jiang, Jinfeng Kang, H.-s. Philip Wong

    Abstract:

    3d vertical RRAM scaling limit is investigated. 3d RRAM functionality along with a viable write/read scheme for the 3d Array are experimentally demonstrated for the first time, using plane electrode with thickness ™ down to 5 nm to minimize 3d stack height. Through 3d circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D Array can scale further to F=13 nm, 3d Array device density is 11× higher than a 2D Array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3d Array. To enlarge 3d Array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.