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Luca P Carloni – One of the best experts on this subject based on the ideXlab platform.

  • system level memory optimization for high level synthesis of component based socs
    International Conference on Hardware Software Codesign and System Synthesis, 2014
    Co-Authors: Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P Carloni

    Abstract:

    The design of specialized Accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an Accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an Accelerator. To address these limitations, we present a novel methodology to automatically derive the memory sub-systems of SoC Accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the Accelerator specifications. We illustrate its effectiveness by presenting experimental results on the design of two Accelerators for a high-performance embedded application.

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David Brooks – One of the best experts on this subject based on the ideXlab platform.

  • Research Infrastructures for Hardware Accelerators
    , 2015
    Co-Authors: Yakun Sophia Shao, David Brooks

    Abstract:

    Abstract Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and Accelerators, computer architects must add Accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on Accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas. Table of Contents: Preface / Acknowledgments / Why Accelerators, Now? / A Taxonomy of Accelerators. / Accelerator Design Flow 101. / Accelerator Modeling / Workload Characterization for Acce…

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  • aladdin a pre rtl power performance Accelerator simulator enabling large design space exploration of customized architectures
    International Symposium on Computer Architecture, 2014
    Co-Authors: Yakun Sophia Shao, Gu-yeon Wei, Brandon Reagen, David Brooks

    Abstract:

    Hardware specialization, in the form of Accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in Accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance Accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of Accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of Accelerators in an SoC environment

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  • The Accelerator store: A shared memory framework for Accelerator-based systems
    ACM Transactions on Architecture and Code Optimization, 2012
    Co-Authors: Michael J. Lyons, Mark Hempstead, Gu-yeon Wei, David Brooks

    Abstract:

    This paper presents the many-Accelerator architecture, a design approach combining the scalability of homogeneous multi-core architectures and system-on-chip’s high performance and power-efficient hardware Accelerators. In preparation for systems containing tens or hundreds of Accelerators, we characterize a diverse pool of Accelerators and find each contains significant amounts of SRAM memory (up to 90p of their area). We take advantage of this discovery and introduce the Accelerator store, a scalable architectural component to minimize Accelerator area by sharing its memories between Accelerators. We evaluate the Accelerator store for two applications and find significant system area reductions (30p) in exchange for small overheads (2p performance, 0p–8p energy). The paper also identifies new research directions enabled by the Accelerator store and the many-Accelerator architecture.

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Christian Pilato – One of the best experts on this subject based on the ideXlab platform.

  • system level memory optimization for high level synthesis of component based socs
    International Conference on Hardware Software Codesign and System Synthesis, 2014
    Co-Authors: Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P Carloni

    Abstract:

    The design of specialized Accelerators is essential to the success of many modern Systems-on-Chip. Electronic system-level design methodologies and high-level synthesis tools are critical for the efficient design and optimization of an Accelerator. Still, these methodologies and tools offer only limited support for the optimization of the memory structures, which are often responsible for most of the area occupied by an Accelerator. To address these limitations, we present a novel methodology to automatically derive the memory sub-systems of SoC Accelerators. Our approach enables compositional design-space exploration and promotes design reuse of the Accelerator specifications. We illustrate its effectiveness by presenting experimental results on the design of two Accelerators for a high-performance embedded application.

    Free Register to Access Article