The Experts below are selected from a list of 4260 Experts worldwide ranked by ideXlab platform
Kwangting Cheng - One of the best experts on this subject based on the ideXlab platform.
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A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastras-montano, Siddharth Gaba, Melika Payvand, Luke Theogarajan, Kwangting ChengAbstract:Recent advances in Access-Transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in Access-Transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.
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toward large scale Access Transistor free memristive crossbars
Asia and South Pacific Design Automation Conference, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastrasmontano, Kwangting ChengAbstract:Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell Access-Transistor may no longer be necessary. However, the elimination of the Access-Transistor introduces several parasitic effects due to the existence of partially-selected devices during memory Accesses, which could limit the scalability of Access-Transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstraction.
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ASP-DAC - Toward large-scale Access-Transistor-free memristive crossbars
The 20th Asia and South Pacific Design Automation Conference, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastras-montano, Kwangting ChengAbstract:Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell Access-Transistor may no longer be necessary. However, the elimination of the Access-Transistor introduces several parasitic effects due to the existence of partially-selected devices during memory Accesses, which could limit the scalability of Access-Transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstraction.
Michael R. Melloch - One of the best experts on this subject based on the ideXlab platform.
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A vertically integrated bipolar storage cell in 6H silicon carbide for nonvolatile memory applications
IEEE Electron Device Letters, 1994Co-Authors: W. Xie, J.a. Cooper, Michael R. Melloch, John W. Palmour, C. H. CarterAbstract:A vertically integrated one Transistor memory cell, in which an n-p-n bipolar Access Transistor is merged with a p-n-p storage capacitor, based on the wide-bandgap semiconductor silicon carbide (SiC), results in a greatly reduced thermal generation rate. Extrapolation of charge recovery data obtained at elevated temperatures suggests a room temperature recovery time of over 10/sup 6/ years. >
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Characterization of a GaAs/AlGaAs modulation‐doped dynamic random Access memory cell
Applied Physics Letters, 1992Co-Authors: J. S. Kleine, J.a. Cooper, Michael R. MellochAbstract:We report the electrical properties of a GaAs dynamic random Access memory (DRAM) cell in which the storage capacitor is a modulation‐doped heterojunction and the Access Transistor is a modulation‐doped field‐effect Transistor. Experimental waveforms illustrating both reading and writing are exhibited. Isolated storage capacitors have 1/e storage times as long as 4.3 h at room temperature. The complete DRAM cell exhibits a room temperature storage time of about 3 min, limited by gate leakage in the Access Transistor.
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GaAs gate dynamic memory technology
1992Co-Authors: Michael R. Melloch, James A. CooperAbstract:Abstract : The expected performance characteristics of GaAs dynamic memories are compared with the capabilities of existing technologies to establish a speed- capacity window for possible applications. The design of GaAs dynamic memories using FET direct-Access of PN-junction-based storage capacitors is developed. The leakage mechanisms in PN-junction capacitors are considered theoretically, and experimental performance of mesa-isolated capacitors in GaAs and AlGaAs is reported. Optimization of storage-time performance and charge capacity by selection of materials and dopings is discussed, and the limitations of optimized capacitors with respect to temperature and scaling are examined experimentally, MBE-grown mesa-isolated PN-junction capacitors are demonstrated to have both sufficient storage time and sufficient capacity for high-density GaAs DRAMs operating above 100C. Design of Access Transistors for optimal subthreshold performance is discussed. A two-dimensional harmonic solution for the potential in subthreshold FETs is presented. The harmonic solution is used to calculate the relationships between physical FET design parameters and subthreshold performance. Trade-offs between design for best subthreshold characteristics versus manufacturability and circuit requirements are considered. The design of complete DRAM cells combining a capacitor and an Access Transistor is developed. Required operating voltages for read, write, and storage sequences are established. The advantages and disadvantages of candidate cell configurations and fabrication techniques are discussed. Experimental demonstration of complete GaAs dynamic memory cells operating at well above room temperature is presented.
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A vertically integrated GaAs bipolar dynamic RAM cell with storage times of 4.5 h at room temperature
IEEE Electron Device Letters, 1992Co-Authors: T.b. Stellwag, J.a. Cooper, Michael R. MellochAbstract:The storage times of FET-Accessed GaAs dynamic RAM cells are limited to less than 1 min at room temperature by gate leakage in the Access Transistor. These Transistor leakage mechanisms have been eliminated by designing a vertically integrated DRAM cell in which an n-p-n bipolar Access Transistor is merged with a p-n-p storage capacitor. Storage times of 4.5 h are obtained at room temperature, a 1000-fold increase over the best FET-Accessed cells. >
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A vertically integrated GaAs bipolar/FET DRAM cell with internal gain
IEEE Electron Device Letters, 1992Co-Authors: Z. G. Ling, J.a. Cooper, Michael R. MellochAbstract:The authors describe a novel dynamic memory cell incorporating a p-n junction storage capacitor, bipolar write-Access Transistor (BJT), and a junction field-effect Transistor (JFET) for nondestructive readout with internal gain. The bipolar Transistor is vertically integrated over the storage capacitor and the JFET is formed from the base region of the BJT. Internal gain improves the signal-to-noise ratio and eliminates the requirement that a specific number of electrons be stored in the cell for reliable readout. >
Amirali Ghofrani - One of the best experts on this subject based on the ideXlab platform.
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A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastras-montano, Siddharth Gaba, Melika Payvand, Luke Theogarajan, Kwangting ChengAbstract:Recent advances in Access-Transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in Access-Transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.
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toward large scale Access Transistor free memristive crossbars
Asia and South Pacific Design Automation Conference, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastrasmontano, Kwangting ChengAbstract:Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell Access-Transistor may no longer be necessary. However, the elimination of the Access-Transistor introduces several parasitic effects due to the existence of partially-selected devices during memory Accesses, which could limit the scalability of Access-Transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstraction.
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ASP-DAC - Toward large-scale Access-Transistor-free memristive crossbars
The 20th Asia and South Pacific Design Automation Conference, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastras-montano, Kwangting ChengAbstract:Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell Access-Transistor may no longer be necessary. However, the elimination of the Access-Transistor introduces several parasitic effects due to the existence of partially-selected devices during memory Accesses, which could limit the scalability of Access-Transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstraction.
J.a. Cooper - One of the best experts on this subject based on the ideXlab platform.
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A vertically integrated bipolar storage cell in 6H silicon carbide for nonvolatile memory applications
IEEE Electron Device Letters, 1994Co-Authors: W. Xie, J.a. Cooper, Michael R. Melloch, John W. Palmour, C. H. CarterAbstract:A vertically integrated one Transistor memory cell, in which an n-p-n bipolar Access Transistor is merged with a p-n-p storage capacitor, based on the wide-bandgap semiconductor silicon carbide (SiC), results in a greatly reduced thermal generation rate. Extrapolation of charge recovery data obtained at elevated temperatures suggests a room temperature recovery time of over 10/sup 6/ years. >
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Characterization of a GaAs/AlGaAs modulation‐doped dynamic random Access memory cell
Applied Physics Letters, 1992Co-Authors: J. S. Kleine, J.a. Cooper, Michael R. MellochAbstract:We report the electrical properties of a GaAs dynamic random Access memory (DRAM) cell in which the storage capacitor is a modulation‐doped heterojunction and the Access Transistor is a modulation‐doped field‐effect Transistor. Experimental waveforms illustrating both reading and writing are exhibited. Isolated storage capacitors have 1/e storage times as long as 4.3 h at room temperature. The complete DRAM cell exhibits a room temperature storage time of about 3 min, limited by gate leakage in the Access Transistor.
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A vertically integrated GaAs bipolar dynamic RAM cell with storage times of 4.5 h at room temperature
IEEE Electron Device Letters, 1992Co-Authors: T.b. Stellwag, J.a. Cooper, Michael R. MellochAbstract:The storage times of FET-Accessed GaAs dynamic RAM cells are limited to less than 1 min at room temperature by gate leakage in the Access Transistor. These Transistor leakage mechanisms have been eliminated by designing a vertically integrated DRAM cell in which an n-p-n bipolar Access Transistor is merged with a p-n-p storage capacitor. Storage times of 4.5 h are obtained at room temperature, a 1000-fold increase over the best FET-Accessed cells. >
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A vertically integrated GaAs bipolar/FET DRAM cell with internal gain
IEEE Electron Device Letters, 1992Co-Authors: Z. G. Ling, J.a. Cooper, Michael R. MellochAbstract:The authors describe a novel dynamic memory cell incorporating a p-n junction storage capacitor, bipolar write-Access Transistor (BJT), and a junction field-effect Transistor (JFET) for nondestructive readout with internal gain. The bipolar Transistor is vertically integrated over the storage capacitor and the JFET is formed from the base region of the BJT. Internal gain improves the signal-to-noise ratio and eliminates the requirement that a specific number of electrons be stored in the cell for reliable readout. >
Miguel Angel Lastras-montano - One of the best experts on this subject based on the ideXlab platform.
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A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastras-montano, Siddharth Gaba, Melika Payvand, Luke Theogarajan, Kwangting ChengAbstract:Recent advances in Access-Transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in Access-Transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.
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ASP-DAC - Toward large-scale Access-Transistor-free memristive crossbars
The 20th Asia and South Pacific Design Automation Conference, 2015Co-Authors: Amirali Ghofrani, Miguel Angel Lastras-montano, Kwangting ChengAbstract:Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell Access-Transistor may no longer be necessary. However, the elimination of the Access-Transistor introduces several parasitic effects due to the existence of partially-selected devices during memory Accesses, which could limit the scalability of Access-Transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstraction.
